Distributed Clock Tree Network for Multi-Die IC Packages

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Solution Overview

Problem

Conventional clock distribution networks are not suitable for 2.5D and 3D integrated circuit packages due to undesirable clock skew, and they do not allow for independent testing of individual dies in multi-die devices.

Innovation Solution

A distributed clock tree structure is implemented in multi-die integrated circuit packages, where each die has its own clock source and tree, coupled through interconnects to form a global clock tree network, allowing each die to be driven by any clock source and enabling independent testing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional clock distribution network is used in 2.5D and 3D IC packages, then the clock signal can be distributed to multiple dies, but undesirable clock skew occurs

Engineering Contradiction:
Improveclock signal distribution reliabilityVSAvoidclock skew
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The clock distribution network is divided into multiple independent clock trees, with each die having its own local clock tree and clock source. This segmentation allows each die to be independently clocked, eliminating the clock skew problem that occurs in conventional distributed networks where a single clock source must serve multiple dies at different physical locations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each die is equipped with its own clock source and local clock tree, providing localized clock distribution optimized for that specific die's geometry and requirements. This local quality approach ensures that clock signals are generated and distributed within each die rather than being transmitted across multiple dies, thereby minimizing clock skew.

Inventive Principle:
Principle #3Local quality

2Reliability

If a conventional clock distribution network is used in multi-die devices, then clock signals can be transmitted across dies, but independent testing of individual dies is not allowed

Engineering Contradiction:
Improvedie-level testabilityVSAvoidindependent die testing capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The clock distribution system is segmented into independent clock trees for each die, allowing individual isolation and testing. Each die's clock tree can be independently activated or deactivated, enabling test engineers to test one die at a time without interference from other dies in the package.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The clock network incorporates dynamic control mechanisms that allow selective activation of different clock sources and trees. This dynamic capability enables the system to switch between different testing modes, including independent die-level testing and full-package operation, thereby providing both testability and operational flexibility.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If multiple clock sources are used in different dies, then independent die operation is enabled, but clock tree network complexity increases

Engineering Contradiction:
Improvemulti-clock source operationVSAvoidclock tree network structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The clock tree network is designed with universal interconnect structures that can accommodate multiple clock sources while maintaining a consistent architectural pattern. The interconnect layer provides standardized interfaces that simplify the integration of multiple clock sources, reducing the overall complexity despite the increased functionality.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The interconnect layer acts as an intermediary between multiple independent clock sources and the various clock trees. This intermediary structure provides a standardized interface and routing mechanism that simplifies the management of multiple clock sources, allowing them to operate independently while maintaining system-level coherence.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9030253B1Integrated circuit package with distributed clock network
Publication Date: 2015.05.12 TAHOE RES LTD
  • US9030253B1 patent drawing
  • US9030253B1 patent drawing
  • US9030253B1 patent drawing

AI summary

Integrated circuit (IC) packages with multiple clock sources are disclosed. A disclosed IC package includes a first die having a first clock source and a first clock tree and a second die having a second clock source and a second clock tree. The first clock source and the second clock source may be coupled to the second clock tree and the first clock tree, respectively, through a plurality of interconnects to form a clock tree network on the IC package. The clock tree network may be operable to be driven by either the first clock source or the second clock source.