Distributed CLPC Gain Control for Stable mmWave EIRP

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Solution Overview

Problem

Existing single-stage closed-loop power control systems for mmWave phase-array integrated circuits fail to maintain target Effective Isotropically Radiated Power (EIRP) due to limited digital-to-analog converter (DAC) gain range, especially when temperature increases rapidly, leading to EIRP reduction.

Innovation Solution

A multi-stage closed-loop power control system with a centralized or distributed architecture, utilizing multiple processors and variable gain amplifiers to adjust analog and digital gains based on accumulated errors, ensuring the system meets the target EIRP across varying temperatures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single-stage CLPC system adjusts only DAC gain, then the system structure remains simple, but the system fails to meet target EIRP when temperature rapidly increases due to limited DAC gain range

Engineering Contradiction:
Improvesystem structureVSAvoidtarget EIRP maintenance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent divides the single-stage CLPC system into two independent stages: a first CLPC system that adjusts DAC gain for coarse power control, and a second CLPC system that adjusts VGA gain for fine power control. This segmentation allows each stage to operate within its optimal gain range, enabling the system to meet target EIRP even during rapid temperature increases while maintaining manageable structural complexity through modular design.

Inventive Principle:
Principle #1Segmentation

2Reliability

If a multi-stage CLPC system with VGA gain adjustment is implemented, then target EIRP is maintained across wider temperature ranges, but system complexity and command overhead increase

Engineering Contradiction:
Improvetarget EIRP maintenanceVSAvoidsystem architecture
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the two CLPC systems into a unified distributed architecture where the power detector shares a common interface with both the first and second processors. The first processor handles DAC gain control while the second processor handles VGA gain control, but both operate under a single distributed control framework that reduces command overhead and simplifies the overall system architecture compared to fully independent multi-stage systems.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If distributed CLPC architecture is used, then command overhead is reduced and system performance is improved, but coordination between multiple processors becomes more complex

Engineering Contradiction:
Improvecommand overhead efficiencyVSAvoidprocessor coordination
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a distributed control framework that acts as an intermediary between the first and second processors. This framework enables the processors to coordinate their gain adjustments independently without direct communication between them, reducing coordination complexity while maintaining the performance benefits of the multi-stage architecture. The framework manages the accumulated error distribution and ensures consistent system operation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11870512B2Distributed closed-loop power control with VGA gain update
Publication Date: 2024.01.09 SAMSUNG ELECTRONICS CO LTD
  • US11870512B2 patent drawing
  • US11870512B2 patent drawing
  • US11870512B2 patent drawing

AI summary

A closed-loop power control (CLPC) system is disclosed that includes a first signal path for a first polarization and a second signal path for a second polarization. The first signal path includes a first power amplifier, a first output power detector configured to detect a first output power level of the first power amplifier, and a first processor configured to determine a first analog gain for a first controller and a first gain for a first digital-to-analog converter based on a first accumulated error between the first output power level and a target Effective Isotropically Radiated Power. A second processor is configured to set a first variable gain of a first variable gain amplifier coupled to an input of the first power amplifier. The CLPC can be configured to control the gain of the first signal path separately or as one signal path.