Distributed CoDec for IC Test Compression
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Solution Overview
Problem
As integrated circuits increase in size and complexity, traditional Test Compression methods face challenges in efficiently routing scan wiring due to high compression ratios, leading to congestion and increased test time, necessitating a more efficient and predictable method for distributed test compression and decompression logic.
Innovation Solution
The implementation of a distributed Compressor-Decompressor (CoDec) system using XOR gates and encoders across a 2-dimensional grid layout, where scan chains are XOR'd together to form single outputs for rows and columns, reducing wire length and congestion by distributing the compression and decompression logic across the chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional centralized Compressor-Decompressor logic is used to achieve test compression, then compression functionality is provided, but scan wiring congestion increases and routing becomes infeasible for high compression ratios
Solution Approach 1:
The patent divides the centralized Compressor-Decompressor logic into multiple distributed CoDec units across the chip. Each CoDec unit handles a portion of the scan chains, segmenting the compression functionality. This segmentation distributes the scan wiring load across multiple locations rather than concentrating all wiring at a single centralized logic block, thereby reducing wiring congestion and making high compression ratios feasible.
Solution Approach 2:
The patent transitions from a centralized single-point compression architecture to a distributed multi-point compression architecture spread across the chip's two-dimensional layout. By distributing CoDec units across different spatial locations on the chip, the scan wiring is routed to multiple nearby destinations rather than all converging to one location, reducing routing complexity and congestion in the scan wiring layer.
2Reliability
If scan chains are loaded 1 bit per clock cycle to ensure proper testing, then test coverage is maintained, but test time increases significantly for long scan chains
Solution Approach 1:
The patent segments long scan chains into multiple shorter scan chains by distributing the scan cells across multiple CoDec units. Each CoDec unit manages its own set of scan chains, which are shorter in length. This segmentation allows the test data to be loaded more quickly since each individual scan chain requires fewer clock cycles to load, while still maintaining comprehensive test coverage across the entire chip.
Solution Approach 2:
The patent enables continuous flow decompression where the distributed CoDec units can load test data into their respective scan chains simultaneously and continuously. Multiple CoDec units operate in parallel, loading their scan chains concurrently, which maintains continuous useful action during the test data application phase, thereby reducing overall test time while preserving test coverage.
3Loss of time
If the number of scan chains is increased to reduce chain length, then test data volume decreases, but scan wiring congestion increases due to more wires terminating at centralized logic
Solution Approach 1:
The patent segments the scan chain management function across multiple distributed CoDec units rather than using a single centralized unit. Each CoDec unit handles a subset of scan chains locally, so the scan wiring terminates at multiple distributed locations across the chip rather than all converging at one point. This segmentation reduces the density of wiring congestion at any single location while still supporting a large total number of scan chains.
Solution Approach 2:
The patent implements local compression and decompression functionality at each CoDec unit, allowing scan chains to be managed locally rather than centrally. Each CoDec unit has its own compression and decompression logic positioned near the scan chains it serves, creating local quality in the sense that each region of the chip has self-contained test functionality. This local arrangement reduces scan wiring congestion by eliminating the need for all scan wires to traverse the entire chip to reach a centralized logic block.
Data Source
AI summary
A CoDec in a design for test integrated circuit. In embodiments described herein, portions of the CoDec are distributed over the area of the IC. In particular, both the compressor and the decompressor may be distributed over the IC. To this end, XOR gates are located locally to the scan chains over the area of the chip to reduce wire length back to the input/output test pins. The compressor and decompressor may be distributed in a 2-dimensional grid. The compressor may XOR each scan chain in two different directions such that a fault may be resolved back to a specific region of the IC.