Distributed Control Clock Synchronization to Reduce Compensating Currents
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Solution Overview
Problem
Decentralized control devices operating with unsynchronized control clocks lead to increased compensating currents, power losses, and noise emissions, and centralized synchronization methods restrict flexibility and increase data traffic.
Innovation Solution
Decentralized control devices synchronize their internal control clocks using a synchronization clock provided by a master device, adjusting their own clocks to align with the external synchronization clock, allowing independent control signal generation while minimizing clock differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If decentralized control devices operate with their own internal control clocks independently, then control flexibility and reaction time are maintained, but compensating currents, power losses, and noise emissions increase
Solution Approach 1:
The patent merges the clock generation functions of decentralized control devices by having them synchronize to a common reference clock signal. Each control device generates its own control signals independently but aligns its timing to the reference clock, combining the benefits of decentralized control with synchronized operation to reduce power losses and interference while maintaining control flexibility.
2Reliability
If a central master controller is used to generate output signals for all decentralized control devices, then synchronization is achieved and interference is reduced, but data traffic increases and computing power requirements increase
Solution Approach 1:
The patent extracts the clock generation function from the central master controller and assigns it to individual control devices. Each control device receives only the reference clock signal and generates its own control signals locally, removing the burden of generating and distributing all control signals from the central controller, thereby reducing data traffic while maintaining synchronization.
3Loss of energy
If decentralized control devices are synchronized to a common clock, then compensating currents and power losses are reduced, but control devices can no longer be deliberately controlled with desired phase shifts
Solution Approach 1:
The patent implements dynamic phase shift capability where control devices can adjust their control signals' phase relative to the reference clock based on operational requirements. The synchronization to the common reference clock is maintained, but flexible phase adjustment is enabled through dynamic control parameters, allowing both energy efficiency and adaptability.
4Speed
If decentralized control devices operate independently without synchronization, then control speed and reaction time are maintained, but noise emissions and magnetic coupling increase
Solution Approach 1:
The patent applies preliminary synchronization action by aligning all control devices to the reference clock before operation begins. This preliminary timing alignment prevents the generation of harmful noise and magnetic coupling effects that would otherwise occur during operation, while maintaining the fast reaction times of decentralized control throughout the operational phase.
Data Source
Figure 1~2
AI summary
The present invention relates to a method and to a device for synchronising decentralised control devices, which each generate and emit control signals clocked in accordance with their own internal control clock, and to a system having decentralised control devices of this kind. According to the invention, a synchronisation clock is provided by one control device to the other control devices, wherein each of the the other control devices that receive the synchronisation clock determine a clock difference between the provided synchronisation clock and their own internal control clock and, depending on the determined clock difference their own internal control clocks are each speeded up and/or slowed down, in order to thus align their own internal control clocks with the external synchronisation clock.