Distributed Controller System for Flash Memory Adaptability
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Solution Overview
Problem
Flash memory devices have fixed controller designs that limit their flexibility and adaptability to different applications, making it difficult to reconfigure or update them for various uses.
Innovation Solution
A distributed controller system is introduced, where control functions are divided among multiple controllers, including an analog controller, a data cache controller, and a master controller, allowing for flexible voltage generation and operation management, enabling adaptation to different applications by updating only the specific controller's software/firmware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed controller design is used in flash memory devices, then the device structure is simple and manufacturing is easier, but the flexibility and adaptability to different applications are limited
Solution Approach 1:
The controller system is divided into multiple independent controller circuits, each responsible for specific control functions. This segmentation allows individual controllers to be updated or reconfigured without affecting the entire system, thereby improving adaptability while managing complexity through functional separation.
Solution Approach 2:
The controller circuits are designed with updateable software/firmware capabilities, allowing the system to dynamically adapt to different applications. This dynamic characteristic enables the same hardware structure to serve multiple purposes by loading different control algorithms, resolving the contradiction between fixed structure and flexible functionality.
2Adaptability or versatility
If control functions are distributed among multiple controllers, then flexibility and adaptability are improved, but the device complexity increases
Solution Approach 1:
Each controller circuit is designed with universal capabilities to handle multiple control functions. Rather than requiring specialized controllers for each function, the universal design allows a single controller to perform various roles depending on the loaded software/firmware, reducing the number of controller circuits needed while maintaining flexibility.
Solution Approach 2:
Multiple control functions are merged into shared controller circuits that can be dynamically reconfigured. This combining approach reduces the total number of controller components while maintaining the ability to perform diverse functions through software/firmware updates, thereby improving flexibility without proportionally increasing hardware complexity.
3Productivity
If a centralized controller is used, then the control logic is unified and easier to manage, but the execution speed of algorithms is slower due to operation overhead
Solution Approach 1:
The centralized control logic is segmented across multiple controller circuits, each handling specific control tasks independently. This parallel processing capability eliminates the sequential operation overhead of centralized controllers, improving algorithm execution speed while distributing software complexity across multiple manageable components.
Solution Approach 2:
Controller circuits are coupled to memory array blocks through intermediary coupling mechanisms that enable direct control without requiring all commands to pass through a single centralized point. This intermediary architecture reduces operation overhead and execution delays while maintaining coordinated control through standardized interface protocols.
Data Source
AI summary
Apparatus including a memory array further include an analog voltage generation circuit, an analog controller, a data cache, a data cache controller, and a master controller. The master controller is configured to generate an indication in response to an interpreted command. The analog controller is configured to determine, in response to the indication, what analog voltages should be generated by the analog voltage generation circuit for the apparatus to perform the interpreted command. The data cache controller is configured to determine, in response to the indication, whether the data cache should be configured to accept data from the memory array or to provide data to the memory array for the apparatus to perform the interpreted command.