Distributed Coulomb Counting with AFE Sample Accumulation

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Solution Overview

Problem

Existing coulomb counters face challenges in accurately measuring charge transfer due to inaccuracies in current and time measurements, limited bandwidth in communication connections, and instability in synchronization between analog front end (AFE) circuits and host microcontrollers, leading to less precise determination of system power output, remaining capacity, and state of charge.

Innovation Solution

Implementing an AFE circuit with a programmable gain amplifier (PGA), automatic gain control (AGC), and message-based communication with a host microcontroller to offload timing and improve accuracy, using a precision crystal oscillator for timing, and robust message-based communication to enhance data handling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the AFE circuit uses its own clock for timing, then the sampling frequency can be increased, but the measurement precision of time deteriorates due to less accurate clock compared to host microcontroller

Engineering Contradiction:
Improvesampling frequencyVSAvoidtime measurement precision
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent uses a DC-isolated bus as an intermediary communication channel between the AFE circuit and host microcontroller. The AFE circuit accumulates current measurements using its own clock, then transfers the accumulated data and sample count via the DC-isolated bus to the host microcontroller, which performs the final charge transfer calculation using its more accurate clock. This mediator approach allows the AFE to operate at high sampling rates while the host microcontroller provides precise timing for the final calculation.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If DC-isolated bus is used for communication between AFE and host microcontroller, then voltage level differences can be handled, but the bandwidth is restricted

Engineering Contradiction:
Improvevoltage level compatibilityVSAvoidcommunication bandwidth
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent extracts the timing function from the AFE circuit and relocates it to the host microcontroller. By transferring only the accumulated current data and sample count via the DC-isolated bus, rather than continuous high-speed communication, the restricted bandwidth of the DC-isolated bus becomes sufficient. The host microcontroller then performs the charge transfer calculation using its accurate clock, eliminating the need for high-bandwidth communication.

Inventive Principle:
Principle #2Taking out (Extraction)

3Stability of the object's composition

If message-based communication is used to offload timing, then synchronization stability improves, but communication overhead increases

Engineering Contradiction:
Improvesynchronization stabilityVSAvoidcommunication overhead
Core Design Contradiction:
Stability of the object's compositionVSLoss of time

Solution Approach 1:

The AFE circuit performs preliminary accumulation of current measurements during the interval between host microcontroller requests. It accumulates the sum of current measurements and counts the number of samples using its own clock, then transfers these pre-accumulated values to the host microcontroller via message-based communication. This preliminary action reduces the amount of data that needs to be communicated and processed, minimizing communication overhead while maintaining synchronization stability.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12449482B2Distributed coulomb counter
Publication Date: 2025.10.21 ANALOG DEVICES INT UNLTD CO
  • US12449482B2 patent drawing
  • US12449482B2 patent drawing
  • US12449482B2 patent drawing

AI summary

In an example, a battery management system may include a host microcontroller, which may be operated in accordance with a first clock signal; and a first analog front end (AFE) circuit. The first AFE circuit may be operated in accordance with a second clock signal that may be unsynchronized with the first clock signal. The first AFE circuit may also include first digital circuitry to (1) accumulate a first value corresponding to a number of ADC sample cycles of the first ADC, and to (2) accumulate a second value corresponding to the digital output representative of the first battery current for the ADC sample cycles accumulated in the first value. The first AFE circuit may transfer a representation of the first value and a representation of the second value to the host microcontroller in response to a request from the host microcontroller.