Distributed Counter Modules for Single-Cycle Multi-Entry Counting
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Solution Overview
Problem
Current counters in integrated circuits are either costly due to their design or inefficient in handling multiple counting entries with high application rates, as they require multiple clock periods to complete a counting operation, limiting their scalability and speed.
Innovation Solution
A counter design comprising multiple counting modules with shared counting spaces and an accumulating module, along with a poll counting mechanism, allows for simultaneous counting across multiple entries within a single clock period, expanding read-write bandwidth and enhancing counting performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If counters are constructed by register, then refreshing rate is high and multiple counting applications can be responded, but cost is high and not suitable for large-scale application
Solution Approach 1:
The counter is divided into multiple counting modules (first counting module, second counting module, etc.), each handling specific counting applications. This segmentation allows parallel processing of multiple counting tasks while using simpler, more cost-effective circuitry in each module, resolving the contradiction between high refreshing rate and low cost.
Solution Approach 2:
Each counting module is designed to handle multiple counting application sources universally. The modules can respond to different counting applications (first counting application, second counting application, etc.) using the same basic counting mechanism, reducing overall system cost while maintaining high productivity.
2Device complexity
If counters are constructed by on-chip RAM, then cost is low and large-scale counting entries can be constructed, but counting operation requires at least four clock periods and processing rate is limited
Solution Approach 1:
The counting system is segmented into multiple independent counting modules that can operate in parallel. Instead of using a single RAM-based counter that requires sequential operations, multiple modules process different counting applications simultaneously, reducing the total clock periods needed and improving processing rate while maintaining low cost.
Solution Approach 2:
Multiple counting modules are merged into a unified counter system that shares common resources while maintaining parallel processing capability. The modules are combined such that their individual counting operations contribute to the overall counting function, achieving both low cost and high processing rate.
3Device complexity
If single counting module is used, then device complexity is low, but read-write bandwidth is insufficient for high-rate counting applications
Solution Approach 1:
The single counting module is segmented into multiple parallel counting modules, each with its own read-write capabilities. This segmentation increases the total read-write bandwidth of the system while keeping individual module complexity low, resolving the contradiction between device complexity and productivity.
Data Source
AI summary
A counter includes: a computing module (100) and N counting modules (101). Each counting module includes a plurality of counting spaces corresponding to different counting entries, and counting spaces of the same counting entry in different counting modules have the same address, wherein the counting module is arranged to provide a value for computing to the computing module in response to a counting application of a counting application source. The computing module is arranged to read values of the same counting entry in different counting modules and accumulate the read values to obtain a total count value of the counting entry, N being an integer not less than 1. Also disclosed is a counting method.