Distributed Sequential Decompression Logic for VLSI Test
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Solution Overview
Problem
The increasing complexity of integrated circuits and the need for higher compression ratios in test data lead to wiring congestion and physical limitations in chip layout, making it difficult to implement efficient decompression logic for test patterns, especially as the number of scan chains and wires increases.
Innovation Solution
A distributed sequential decompression logic is implemented using a 2-dimensional grid on the integrated circuit, where XOR gates are placed across the grid to distribute decompression tasks, reducing wire length and congestion by assigning even and odd term combinations to different dimensions and using cyclic shift registers to manage data flow efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional global scan wiring is used to connect decompression logic to scan chains, then decompression functionality is achieved, but wiring congestion and chip area increase as compression ratio increases
Solution Approach 1:
The decompression logic is segmented into multiple independent XOR trees distributed across the chip. Each XOR tree handles a portion of the scan chains, dividing the monolithic decompression function into modular units. This segmentation reduces wiring congestion at any single location and allows parallel operation, enabling higher compression ratios without proportional increases in chip area.
Solution Approach 2:
The patent transitions from a single centralized decompression location to a two-dimensional distributed arrangement of XOR trees across the chip. By spreading the decompression logic across multiple spatial dimensions rather than concentrating it in one corner, the design accommodates higher compression ratios while maintaining reasonable wire lengths and reducing local congestion.
2Reliability
If more scan chains are used to increase compression ratio, then test coverage improves, but wire length and congestion increase
Solution Approach 1:
Scan chains are grouped into multiple groups, with each XOR tree receiving inputs from a specific subset of scan chains. This segmentation creates localized connection regions, reducing the average wire length from centralized decompression points and minimizing congestion in any single area while maintaining comprehensive test coverage.
Solution Approach 2:
Each XOR tree is positioned locally to serve its associated group of scan chains, creating localized decomposition regions. This local quality approach ensures that wires connecting scan chains to their designated XOR tree are relatively short, reducing overall wire length and congestion while still achieving high compression ratios through the collective operation of multiple trees.
Data Source
AI summary
Methods, systems, and integrated circuits for decompressing a set of scan input data in a Design for Test (DFT) application, in which implementation may include determining a number of scan inputs to applied circuit from automated test equipment (ATE). Based on the number of scan inputs, another aspect of implementation may involve generating a 2-dimensional grid on the integrated circuit (IC). Another implementation aspect may involve decompressing the scan inputs from the ATE according to decompression logic that is sequentially distributed such that the grid can locally apply the last stage of the decompression logic. In accordance with aspects of the method, the physical structure of an IC decompression logic is more accessible to individual scan chains and reduces congestion on board the IC.