Distributed Digital LDO Regulator for EM-Safe Light-Load Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Digital low-dropout (DLDO) voltage regulators face challenges in regulating output voltage under varying load currents and dropout levels while maintaining low ripple, high current and power efficiencies, and avoiding fin self-heating (FiSH) and electro-migration (EM) risks, especially under light-load conditions and high dropout scenarios, where traditional DLDO designs often require excessive top metal resources and are difficult to integrate into digital design flows.
Innovation Solution
A distributed DLDO design with primary and secondary power gates, fine-grain clock gating, and a tunable replica circuit with a single time-to-digital converter for both fine-grain and coarse-grain control, using under-drive voltage to reduce EM and FiSH risks, and dynamically adjusting power gate strength to manage load conditions and voltage droops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional DLDO designs use a single power gate to regulate output voltage, then the device complexity is reduced, but the reliability decreases due to excessive current density causing EM and FiSH risks
Solution Approach 1:
The patent divides a single power gate into multiple power gates (first power gate and second power gate) that operate in parallel. This segmentation distributes the current load across multiple devices, reducing current density and eliminating EM and FiSH risks while maintaining voltage regulation functionality.
2Reliability
If DLDO regulators use more metal resources to handle high current densities, then the reliability improves, but the area occupied increases
Solution Approach 1:
By segmenting the power gate into multiple parallel devices, the current handling capability is distributed across several smaller current paths rather than requiring a single high-capacity metal structure, reducing overall metal resource usage.
Solution Approach 2:
The patent applies different characteristics to different power gates - the first power gate operates in linear mode for fine-grain control while the second power gate operates in saturated mode for coarse-grain control, optimizing local performance and resource utilization.
3Measurement precision
If DLDO designs use coarse-grain control only, then the device complexity is reduced, but the measurement precision of voltage regulation decreases
Solution Approach 1:
The control mechanism is segmented into two independent control loops: a fine-grain control loop for precise voltage regulation and a coarse-grain control loop for broader voltage adjustments. This segmentation enables high precision voltage regulation while keeping each control loop relatively simple.
Solution Approach 2:
The system dynamically switches between fine-grain and coarse-grain control modes based on operating conditions, allowing the regulator to achieve high precision when needed while maintaining simplicity under less demanding conditions.
4Use of energy by moving object
If DLDO regulators operate at light load conditions, then the power efficiency improves, but the reliability worsens due to excessive current density in fewer active power gates
Solution Approach 1:
The system dynamically adjusts which power gates are active based on load conditions. At light loads, the control logic ensures that sufficient power gates remain active to maintain acceptable current density, preventing EM and FiSH risks while preserving power efficiency.
Solution Approach 2:
The dual control loops provide continuous feedback about operating conditions, allowing the system to monitor and adjust power gate activation to maintain safe current density levels even at light loads, ensuring reliability without sacrificing efficiency.
Data Source
AI summary
An apparatus is provided which comprises: a first device coupled to a first power supply rail; a second device coupled in series with the first device, wherein the second device is coupled to a second power supply rail; and a third device coupled to the first and second power supply rails, wherein the first device is controllable by a first input, wherein the second device is controllable by a second input, wherein the third device is controllable by a third input, and wherein the first input is an analog bias between a high power supply level and a ground supply level.