Distributed DLL Clock Network for Leaf Node Phase Alignment
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Solution Overview
Problem
Clock distribution networks in integrated circuits face challenges in maintaining phase alignment of localized clocks at leaf nodes due to process, voltage, and temperature variations, leading to inefficiencies with traditional large range delay locked loops that consume more area and power.
Innovation Solution
Implementing a global large range delay locked loop at the root of the system clock and small range delay locked loops in each branch, where the global DLL aligns one leaf node clock to a reference clock, and local small range DLLs continuously compensate for phase mismatches caused by PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional large range delay locked loops are used in each branch to align leaf node clocks, then phase alignment is achieved, but area and power consumption increase
Solution Approach 1:
The clock distribution system is segmented into a hierarchical structure with a global DLL at the root and multiple local DLLs in different branches. Each local DLL handles only its specific branch's clock alignment, dividing the previously monolithic large range DLL functionality into smaller, distributed units that collectively achieve system-wide phase alignment while reducing individual and total area requirements.
Solution Approach 2:
The patent introduces a hierarchical dimension to the clock distribution architecture, organizing DLLs in a tree structure with global and local levels. This dimensional reorganization allows the system to achieve comprehensive clock alignment coverage without requiring large range DLLs in every branch, thereby reducing overall area and power consumption while maintaining reliability.
2Reliability
If traditional large range delay locked loops are used in each branch to align leaf node clocks, then phase alignment is achieved, but power consumption increases
Solution Approach 1:
The power consumption issue is addressed by segmenting the clock alignment functionality into a global DLL and multiple local DLLs. Each local DLL consumes less power than a full large range DLL would require, and the hierarchical structure enables more efficient power distribution and management across the clock network, reducing total power consumption while maintaining phase alignment capability.
Solution Approach 2:
Each local DLL is designed with appropriate delay range characteristics matched to its specific branch requirements rather than using uniform large range DLLs throughout. This local optimization allows each DLL to operate at minimal necessary power levels while achieving the required phase alignment for its designated branch, reducing overall system power consumption.
3Area of stationary object
If a single global DLL is used without local DLLs, then area and power are reduced, but phase alignment under PVT variations deteriorates
Solution Approach 1:
The hierarchical DLL structure segments the clock alignment task into global and local functions. The global DLL provides coarse alignment across the entire system, while local DLLs provide fine-grained adjustment for their respective branches, compensating for local PVT variations that a single global DLL cannot address effectively. This segmentation maintains area efficiency while improving reliability under varying conditions.
Solution Approach 2:
The system dynamically adapts to PVT variations through the coordinated operation of global and local DLLs. The local DLLs can independently adjust their delay elements in response to local temperature, voltage, and process variations, providing dynamic compensation that maintains phase alignment reliability without requiring a monolithic large range DLL structure.
Data Source
AI summary
In an embodiment, a clock distribution circuit includes a global delay locked loop (DLL) configured to receive a global clock input signal (RCLK), a lead/lag input signal and to output a clock signal. The circuit includes a plurality of clock distribution blocks, each clock distribution block configured to receive the output of the global DLL, a lead/lag signal and to output a leaf node clock signal, each clock distribution block further comprises a local DLL. The global DLL is further configured to align one of the leaf node clock signals to a reference clock based on its lead/lag input signal. Each clock distribution block is further configured to align its leaf node clock signal to a reference clock based on its lead/lag signal.