Distributed DMA Adaptor Circuit Reduces Signal Transfer Bottlenecks
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Solution Overview
Problem
Traditional DMA controllers introduce signal transfer bottlenecks and complicate control information distribution, especially when multiple controllers are used, leading to a coarse level of control and inefficiencies in data transfer management.
Innovation Solution
An adaptor circuit with a direct memory access manager that autonomously manages data transfers between peripheral and system devices, providing tailored DMA capabilities and reducing bottlenecks by being physically close to peripheral devices, while maintaining software compatibility with existing architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a traditional DMA controller is used to service DMA requirements of several devices, then the processing burden on the CPU is reduced, but a signal transfer bottleneck is introduced
Solution Approach 1:
The patent divides the centralized DMA controller into multiple distributed DMA controllers, each serving specific peripheral devices. This segmentation reduces the signal transfer bottleneck by eliminating the single point of congestion while maintaining autonomous DMA management for each device.
Solution Approach 2:
Each distributed DMA controller is positioned locally near the peripheral devices it serves, enabling direct and efficient data transfer management. This local placement reduces signal path length and eliminates the need for long signal routes through a central controller.
2Adaptability or versatility
If more than one DMA controller is provided on respective buses, then separate DMA capabilities are provided, but control information distribution becomes complicated
Solution Approach 1:
Each DMA controller is configured to autonomously manage data transfers for its associated peripheral devices without requiring coordination signals from other controllers. This self-service capability simplifies control information distribution while maintaining separate DMA capabilities on different buses.
3Ease of manufacture
If DMA controllers are provided with fixed priority levels and a single memory map, then implementation is simplified, but control precision becomes coarse
Solution Approach 1:
The patent implements dynamic priority assignment and multiple memory maps within each DMA controller, allowing priority levels to be adjusted based on real-time system requirements. This dynamic configuration enables fine-grained control precision while maintaining relatively simple hardware implementation through software-based priority management.
Data Source
AI summary
An adaptor circuit 20 for peripheral devices 14, 18 is provided with a direct memory access manager 38. This local direct memory access manager 38 is able to autonomously manage data transfers on behalf of its associated peripheral device 14, 18. A computer program tools used to generate signal interconnects 24 is used to additionally specify whether a DMA capability is to be provided for a peripheral device 14, 18, whereupon an adaptor circuit 20, 22 including a DMA manager 38 can be included within the signal interconnect. A DMA command signal is added to the interconnect signals being passed around the signal interconnect 24 and enables DMA command/configuration data to be distributed using the existing signal distribution infrastructure and addressed to the associated peripheral device 14, 18 of the target local DMA controller 38. Existing software drivers can issue control information to a main central DMA controller 6, which then passes this information on to a DMA Capable adaptor circuit 20 to manage the transfer concerned. Thus the present technique can be used without requiring software drivers to be rewritten.