Distributed DMA Configuration Across AIE Tiles
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Solution Overview
Problem
Existing methods for configuring direct memory access (DMA) operations in hardware accelerators require significant computational resources, as they rely on a controller to program DMA circuitry across multiple tiles, which can be compute-limited.
Innovation Solution
Implementing DMA circuitry in multiple tiles of a hardware accelerator array that can fetch and configure DMA operations using pointers, allowing parallel execution of DMA operations across columns, reducing the need for a central controller to program each tile individually.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a central controller programs DMA circuitry across multiple tiles individually, then DMA operations can be configured, but the controller's computational resources are significantly consumed
Solution Approach 1:
The patent divides the DMA configuration task into segments by distributing DMA circuitry across multiple tiles (e.g., 32 tiles with DMA circuitry in interface tiles). Each tile's DMA circuitry can be configured independently, allowing the configuration workload to be distributed rather than centralized, thus reducing the computational burden on any single controller.
Solution Approach 2:
The patent enables DMA circuitry in interface tiles to self-configure by fetching and executing DMA operations from local or shared memory. This self-service capability eliminates the need for a central controller to program each DMA unit individually, significantly reducing controller resource consumption while maintaining reliable DMA operation configuration.
2Reliability
If a central controller programs each tile's DMA circuitry individually, then DMA operations can be configured, but the configuration process consumes significant time
Solution Approach 1:
By segmenting the hardware accelerator into multiple independent tiles with their own DMA circuitry, the patent enables parallel configuration of DMA operations across different tiles. This segmentation allows simultaneous programming of multiple DMA units, dramatically reducing the total configuration time compared to sequential programming by a single controller.
Solution Approach 2:
The patent implements preliminary action by pre-loading DMA operation data into memory before execution. The DMA circuitry in interface tiles can fetch these pre-prepared operations directly from memory, eliminating the need for real-time controller intervention during configuration, thus reducing configuration time.
3Productivity
If DMA circuitry is distributed across multiple tiles, then parallel configuration is enabled, but the device complexity increases
Solution Approach 1:
The patent applies universality by making interface tiles serve multiple functions: they act as both computational units and configuration controllers for their respective DMA circuitry. This multi-functionality reduces the need for separate dedicated configuration controllers, thereby managing device complexity while enabling parallel configuration across multiple tiles.
Solution Approach 2:
The patent merges the configuration control function into the existing interface tiles rather than adding separate configuration hardware. By combining DMA execution and configuration capabilities within the same interface tile structure, the patent enables parallel configuration without proportionally increasing overall device complexity.
Data Source
AI summary
Embodiments herein describe using DMA circuitry in multiple tiles in a hardware accelerator array to program the DMA operations within the array. For example, a system on a chip (SoC) may include a controller that is external to the hardware accelerator array. While the controller can be used to program the DMA circuitry within the array, this can be slow since the controller may be compute limited. Instead, the embodiments herein describe techniques where the controller is provided pointers to the register read and write corresponding to the DMA operations. The controller can provide these pointers to multiple DMA engines in the hardware accelerator array (e.g., DMA circuitry in interface tiles) which fetch the DMA operations and program themselves, as well as other DMA circuitry in the array.