Distributed DMA Architecture for Parallel Chip Data Transfer
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Solution Overview
Problem
Conventional DMA technologies in SoC chips face limitations in meeting increasing computing power requirements due to single DMAC processing capabilities and large hardware resource overheads from caching read-back data.
Innovation Solution
An integrated chip with a DMA management module that splits data transfer tasks into subtasks, distributed across multiple DMA agent modules, utilizing a distributed architecture for parallel execution and address translation, reducing the need for large data caches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single DMAC processes data transfer tasks sequentially, then the hardware resource overhead is reduced, but the data transfer efficiency cannot meet increasing computing power requirements
Solution Approach 1:
The patent divides the data transfer task into multiple subtasks and distributes them to multiple DMA agent modules. Each DMA agent module processes a portion of the subtasks in parallel, thereby improving overall data transfer efficiency without requiring a single overly complex DMAC. The DMA management module segments the task and the DMA agent modules execute them concurrently.
2Reliability
If all read-back data is stored in the DMAC, then data transfer completion is ensured, but large data cache resource is required resulting in large hardware overhead
Solution Approach 1:
The patent segments the data transfer process into multiple subtasks distributed across multiple DMA agent modules. Each module handles a portion of the data transfer independently, eliminating the need for a single large data cache to store all read-back data. The distributed architecture reduces the cache requirement at each individual module while maintaining overall data transfer reliability.
Solution Approach 2:
The patent transitions from a centralized data cache approach to a distributed data handling approach across multiple modules. Instead of accumulating all data in a single DMAC's cache, the system distributes data processing across multiple dimensions (multiple DMA agent modules), reducing the cache burden at each dimension while maintaining completeness through coordinated execution.
Data Source
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AI summary
An integrated chip and a data transfer method are provided to meet an increasing computing power requirement of a processor chip. The integrated chip includes a DMA management module and a DMA agent module. The DMA management module is configured to split a data transfer task delivered by a processor into a plurality of subtasks, and deliver the plurality of subtasks to each DMA agent module in a plurality of DMA agent modules. Each DMA agent module in the plurality of DMA agent modules is configured to execute the plurality of subtasks.