Distributed ECC Architecture in Memory Devices for Lower Board Power
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Solution Overview
Problem
Memory systems with system controllers performing error correction coding experience high power consumption and operation temperature due to large data transfer through electrical circuit boards.
Innovation Solution
Implementing error correction code (ECC) circuits in memory devices, such as flash memory, to reduce data transfer through electrical circuit boards, with a smaller impedance connection within the memory device, thereby reducing power consumption and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction coding is performed by the system controller, then data transfer through electrical circuit boards increases, but power consumption and operation temperature increase
Solution Approach 1:
The patent divides the error correction coding function into two segments: a first ECC circuit in the memory device for initial encoding/decoding, and a second ECC circuit in the system controller for enhanced decoding. This segmentation allows the memory device to handle basic error correction locally, reducing data transfer volume and power consumption on the system controller side while maintaining strong error correction capability through the combined approach
Solution Approach 2:
The patent moves the first ECC circuit from the system controller dimension to the memory device dimension. By implementing ECC functionality within the memory device itself, the system reduces the burden on the system controller and electrical circuit boards, thereby reducing power consumption and operation temperature in the system controller while maintaining error correction capability
2Reliability
If error correction coding is performed by the system controller, then data transfer through electrical circuit boards increases, but operation temperature increases
Solution Approach 1:
The patent segments the error correction function between memory device and system controller, with the first ECC circuit handling initial encoding/decoding in the memory device. This reduces the computational burden and heat generation in the system controller while maintaining strong error correction capability through the second ECC circuit's enhanced decoding function
Solution Approach 2:
By relocating the first ECC circuit to the memory device dimension, the patent reduces heat sources in the system controller dimension. The memory device's internal ECC operations generate less heat in the system controller area, improving heat dissipation while maintaining error correction capability through the distributed architecture
3Use of energy by moving object
If ECC circuits are implemented in memory devices, then data transfer through electrical circuit boards is reduced, but device complexity increases
Solution Approach 1:
The patent merges the first ECC circuit with the memory device, combining error correction functionality with storage capabilities in a single integrated unit. This reduces the need for separate error correction hardware in the system controller and reduces data transfer through electrical circuit boards, though it does increase memory device complexity
Solution Approach 2:
The memory device is given multiple functions: data storage and error correction coding/decoding. By making the memory device universal and capable of handling both functions, the patent reduces the need for dedicated error correction hardware elsewhere in the system, reducing power consumption and data transfer requirements
Data Source
AI summary
Methods, devices, systems, and apparatus including computer-readable mediums for managing error correction coding in memory systems are provided. In one aspect, a memory system includes a system controller configured to communicate with a host device, and a memory device coupled to the system controller. The memory device includes at least one memory and a memory controller coupled to the at least one memory. The memory controller includes an error correction code (ECC) circuit configured to perform error correction coding for data received from at least one of the system controller or the at least one memory.