Distributed ECC Circuitry for Parallel Multi-Word Memory Read
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Solution Overview
Problem
Conventional error correction for configuration memory in programmable logic devices is time-consuming, requiring multiple clock cycles for reading and writing data, including error correction bits, which slows down the overall process.
Innovation Solution
The implementation of distributed error correction coding circuitry that allows for parallel access to memory in multiple word increments, enabling inline error checking during data read operations, thereby reducing the time required for error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction is implemented for configuration memory, then error detection and correction capability is improved, but the time required for configuration loading is increased
Solution Approach 1:
The patent applies preliminary action by performing error correction code generation during the configuration data loading process itself, rather than as a separate subsequent step. The ECC circuitry generates check bits concurrently with the loading of configuration data into the device, allowing error correction preparation to occur before the configuration is fully loaded and operational, thus reducing overall configuration time while maintaining reliability
Solution Approach 2:
The patent implements continuity of useful action by ensuring that error correction operations proceed continuously alongside configuration data loading. The ECC circuitry operates in parallel with the configuration loading process, continuously generating check bits as data is loaded, rather than pausing the loading process to perform error correction separately. This continuous operation eliminates idle time and reduces total configuration time
2Reliability
If error correction bits are stored in configuration memory, then data integrity is improved, but the memory capacity available for functional configuration is reduced
Solution Approach 1:
The patent applies segmentation by dividing the configuration memory into separate functional regions: one dedicated to storing configuration data and another for storing error correction check bits. This segmentation allows the memory to be organized such that functional configuration data and error correction data are stored in distinct locations, enabling the system to maintain data integrity through dedicated ECC storage while preserving maximum memory capacity for actual functional configuration purposes
Data Source
AI summary
An integrated circuit that accesses memory from data lines in multiple word increments having distributed error correction coding circuitry is described. The data lines are selectively coupled to a portion of the memory for a read of data stored in the portion of the memory. The read includes providing in parallel in the multiple word increments the data stored in the portion of the memory. The data lines are selectively tapped to provide the data from the read to flow in parallel in a first direction and in a second direction. The first direction provides the data to the data registers, and the second direction provides the data to be propagated in an error checking matrix of the distributed error correction coding circuitry.