Distributed ESD Protection Circuit With Shared Bridge Node Layout

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Solution Overview

Problem

Existing semiconductor devices require extensive area and increased parasitic impedance due to numerous ESD protection circuits, which are necessary for withstanding electrostatic discharge events while maintaining electrical isolation between pads, leading to higher costs and die size.

Innovation Solution

Implementing distributed ESD protection circuits using fewer ESD diodes, with a bridge node acting as a common connection for multiple ESD protection circuits, reducing the number of diodes by half or more and minimizing parasitic impedance, while maintaining effective ESD protection and electrical isolation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ESD protection circuits are placed between every two adjacent pads, then ESD protection capability is improved, but semiconductor die area is increased

Engineering Contradiction:
ImproveESD protection capabilityVSAvoidsemiconductor die area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

Multiple ESD protection circuits share a common connection node instead of being fully isolated. The patent shows that ESD protection circuits connected to adjacent pads can share a common node, merging previously separate circuits into a distributed network that provides protection while reducing redundant components and die area.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The ESD protection function is segmented into distributed circuits connected to individual pads, with each circuit providing localized protection. This segmentation allows the system to maintain overall ESD protection capability while using fewer total components compared to fully isolated circuits.

Inventive Principle:
Principle #1Segmentation

2Reliability

If ESD protection circuits are placed between every two adjacent pads, then ESD protection capability is improved, but parasitic impedance is increased

Engineering Contradiction:
ImproveESD protection capabilityVSAvoidparasitic impedance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

By merging multiple ESD protection circuits through shared common nodes, the patent reduces the total number of isolation elements and connection paths. This merging decreases the cumulative parasitic impedance while maintaining ESD protection capability across all pads.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If numerous ESD diodes are used in ESD protection circuits, then ESD protection capability is improved, but device complexity is increased

Engineering Contradiction:
ImproveESD protection capabilityVSAvoidnumber of ESD diodes
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges ESD protection functions across multiple circuits by sharing common nodes and diodes. Instead of requiring separate diodes for each isolated circuit, the shared architecture allows multiple circuits to utilize the same diode components, significantly reducing the total diode count while maintaining protection capability.

Inventive Principle:
Principle #5Merging (Combining)

4Reliability

If ESD protection circuits are placed between every two adjacent pads, then electrical isolation between pads is maintained, but semiconductor die area is increased

Engineering Contradiction:
Improveelectrical isolation between padsVSAvoidsemiconductor die area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent segments the ESD protection function into distributed circuits that maintain electrical isolation between pads during normal operation. Each segmented circuit provides localized isolation while the overall distributed architecture reduces total area compared to fully isolated circuits.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

By merging circuits through shared nodes, the patent achieves electrical isolation between pads without requiring separate isolated circuits for each pad pair. The shared architecture provides isolation functionality with reduced die area.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20240348046A1Distributed electrostatic discharge protection for semiconductor device
Publication Date: 2024.10.17 SEMICON COMPONENTS IND LLC
  • US20240348046A1 patent drawing
  • US20240348046A1 patent drawing
  • US20240348046A1 patent drawing

AI summary

In a general aspect, a circuit includes a first ESD protection circuit having a first terminal and a second terminal, and a second ESD protection circuit having a first terminal and a second terminal. The second terminal of the second ESD protection circuit is coupled with the second terminal of the first ESD protection circuit. The circuit further includes a third ESD protection circuit having a first terminal and a second terminal. The second terminal of the third ESD protection circuit is coupled with the second terminal of the first ESD protection circuit and the second terminal of the second ESD protection circuit.