Distributed Fault Collection Circuits for Programmable Error Routing
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Solution Overview
Problem
The increasing complexity of processing systems, particularly in automotive applications, leads to inefficiencies in managing a significant number of error signals, which results in increased area requirements for fault collection and management circuits and complex wiring, while also complicating access rights management for software tasks and virtual machines.
Innovation Solution
The processing system is divided into fault collection and management circuits, with error combination circuits near safety monitoring circuits generating combined error signals, and fault management circuits configured to handle these signals efficiently, allowing for separate management of error signals per virtual machine or microprocessor, and enabling precise access control through hardware and software protection mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a centralized fault collection and management circuit is used to manage all error signals, then comprehensive error management is achieved, but the area requirements and wiring complexity increase significantly
Solution Approach 1:
The patent divides the centralized fault collection and management circuit into multiple distributed error combination circuits, each located near specific safety monitoring circuits. These distributed circuits locally combine error signals before forwarding them to a reduced fault management circuit, thereby segmenting the originally centralized system to reduce area requirements while maintaining comprehensive error management capability.
Solution Approach 2:
The patent introduces a hierarchical dimension to the error management architecture by organizing error combination circuits at the local level near safety monitoring circuits, intermediate error management at regional levels, and centralized fault management at the system level. This multi-dimensional organization reduces wiring complexity and area requirements compared to a purely centralized two-dimensional architecture.
2Loss of information
If multiple separate error signals are managed individually, then precise error tracking is achieved, but the wiring complexity and management overhead increase
Solution Approach 1:
The patent merges multiple individual error signals into combined error signals at distributed error combination circuits located near safety monitoring circuits. Each error combination circuit aggregates error signals from multiple sources using logic operations, thereby reducing the number of individual signal paths and wiring complexity while preserving error information completeness through structured combination logic.
Solution Approach 2:
The patent creates universal error combination circuits that can handle multiple types of error signals from different safety monitoring circuits through standardized logic operations. These circuits serve multiple functions: local error aggregation, signal conditioning, and hierarchical forwarding, thereby reducing overall system complexity while maintaining comprehensive error tracking capability.
3Reliability
If access rights to error signals are managed centrally, then security control is achieved, but access efficiency and timeliness decrease for multiple software tasks and virtual machines
Solution Approach 1:
The patent segments the centralized access control mechanism into distributed access control points at each error combination circuit and fault management circuit level. Each segment maintains local access control policies for specific software tasks and virtual machines, enabling parallel access operations that reduce timing delays while preserving security through hierarchical authorization checks.
Solution Approach 2:
The patent implements preliminary access control configurations at the error combination circuits, where access rights for different software tasks and virtual machines are pre-established. This allows software tasks to access error signals through pre-authenticated paths without requiring real-time centralized authorization decisions, thereby reducing access time while maintaining security.
Data Source
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AI summary
A processing system (10a) is described. The processing system comprises a plurality of safety monitoring circuits (SM) configured to generate a plurality of error signals (ERR) by monitoring the operation of a microprocessor, a memory controller and/or a resource. In particular, the processing system comprises a plurality of fault collection subcircuits (32), wherein each fault collection sub-circuit (32) comprises one or more error combination circuits (320). Each error combination circuit (320) comprises a first programmable register (3204) and is configured to receive a subset of the error signals (ERR1, ..., ERRs), determine whether one or more of the error signals (ERR1, ..., ERRs) are asserted and store error status data to the first register (3204), which identifying the one or more asserted error signals (ERR1, ..., ERRs). Moreover, each error combination circuit (320) is configured to read enable data from the first register and generate a combined error signal (CES) as a function of the error status data and the enable data. The error management circuit (34) comprises a second programmable register and is configured to receive the combined error signals (CES), read routing data from the second register and generate for each microprocessor a respective signal (IRQ) used to signal an error as a function of the combined error signals (CES) and the routing data.