Distributed Arithmetic FIR Filter for Low-Power Correlation
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Solution Overview
Problem
Conventional implementations of finite impulse response (FIR) filters require significant power consumption and occupy large space due to the need for numerous multiplier and adder stages, making them costly for signal processing systems.
Innovation Solution
The implementation of an FIR filter using a distributed arithmetic architecture, which reduces the number of high-power components and minimizes the footprint by performing bit-level rearrangement of multiplications and using logic gates instead of multipliers, resulting in a more efficient power and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a conventional MAC architecture is used to implement an FIR filter, then the filter can achieve the required signal processing function, but the power consumption and circuit footprint increase significantly
Solution Approach 1:
The patent segments the multiplication operation into bit-level operations. Instead of performing full-word multiplications using complex multiplier circuits, the distributed arithmetic architecture breaks down each multiplication into individual bit positions, processing one bit at a time through a series of simpler logic stages. This segmentation replaces power-intensive multiplier circuits with lighter-weight logic gates and adders, thereby reducing both power consumption and circuit footprint while maintaining the same filtering function.
Solution Approach 2:
The patent substitutes the mechanical/electrical multiplication operation with a different computational approach based on distributed arithmetic. Instead of using traditional multiplier hardware that directly computes products, the system uses a sequence of logic operations (AND gates, adders, and shift operations) that collectively achieve the same multiplication result. This substitution replaces high-power multiplier circuits with lower-power logic gate implementations, resolving the contradiction between functional requirements and power/area constraints.
2Reliability
If numerous multiplier and adder stages are used to implement an FIR filter, then the filtering function is achieved, but the device complexity and power consumption increase
Solution Approach 1:
The patent segments the filtering function into multiple bit-level processing stages. Each stage processes one bit position of the input signal through a sequence of operations (AND with coefficient bits, addition, and shifting). This segmentation allows the complex filtering function to be achieved through many simple, identical stages rather than fewer complex multiplier-adder units, thereby maintaining filtering reliability while reducing overall device complexity.
Solution Approach 2:
The distributed arithmetic architecture employs periodic action by processing input bits sequentially through repeated cycles of the same operational sequence (AND operation, addition, shift). Each bit position undergoes the same periodic pattern of operations, which simplifies the overall circuit design by using identical reusable logic blocks rather than varying complex components, thus maintaining filtering function while reducing device complexity.
Data Source
AI summary
Provided herein is an implementation of a finite impulse response (FIR) filter that uses a distributed arithmetic architecture. In one or more example, a data sample with multiple bits is processed through a plurality of bit-level multiply and accumulate circuits, wherein each bit of the data sample corresponds to a bit of the data sample. The output of each bit-level multiply and accumulate circuit can then be shifted by an appropriate amount based on the bit placement of the bit of the data sample that corresponds to the bit-level multiply and accumulate circuit. After each output is shifted by the appropriate amount, the outputs can be aggregated to form a final FIR filter result.