Distributed FPGA Data Flow for Host Interface Scaling
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Solution Overview
Problem
Conventional computing systems face limitations in data processing efficiency due to the physical constraints of host interfaces on the number of Field Programmable Gate Array (FPGA) acceleration boards, leading to inefficient data interaction between FPGA acceleration boards.
Innovation Solution
A data processing method and apparatus that divides tasks into subtasks and distributes them across multiple FPGA acceleration boards connected via a network, enabling direct data transmission between boards without relying on a host-side intermediary, using a distributed data flow programming framework with CPU and FPGA stacks for task management and execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data interaction between FPGA acceleration boards is performed through host side using PCIE interface, then data transmission can be achieved, but the data computing efficiency is relatively low and the number of boards is limited by host interfaces
Solution Approach 1:
The patent introduces a network as an intermediary communication channel between FPGA acceleration boards, replacing the traditional host-mediated PCIE communication path. This allows direct peer-to-peer data transmission between boards while maintaining the host's coordination capability, thereby improving computing efficiency and removing interface limitations.
Solution Approach 2:
The patent segments the communication function from the host system by enabling direct network-based communication between FPGA boards. This separation allows the host to focus on task coordination while data transmission occurs independently through network channels, eliminating the bottleneck of host interface capacity.
2Quantity of substance
If multiple FPGA acceleration boards are connected to host side, then more computing resources are available, but the physical limitation of host interfaces restricts the number of supported boards
Solution Approach 1:
The patent transitions from a single-dimension communication architecture (host-centric PCIE connections) to a multi-dimensional architecture by adding network-based communication paths. This allows FPGA boards to communicate not only through the host but also directly with each other via network interfaces, effectively expanding the system's scaling capacity beyond host interface limitations.
3Productivity
If data is transmitted through host side between FPGA boards, then communication can be established, but data processing throughput is reduced due to the intermediary host involvement
Solution Approach 1:
The patent extracts the data transmission function from the host system and relocates it to direct network communication between FPGA boards. This removal of the host intermediary from the data path eliminates the associated delays and bandwidth limitations, allowing faster direct transmission while the host retains control over task distribution and coordination.
Data Source
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AI summary
A data processing method, a data processing apparatus, a distributed data flow programming framework, an electronic device, and a storage medium. The data processing method includes: dividing a data processing task into a plurality of data processing subtasks (S101); determining, in a Field Programmable Gate Array (FPGA) accelerator side, a target FPGA acceleration board corresponding to each of the data processing subtasks (S102); and sending data to be computed to the target FPGA acceleration board, and executing the corresponding data processing subtask by use of each of the target FPGA acceleration boards to obtain a data processing result (S 103). According to the method, a physical limitation of host interfaces on the number of FPGA acceleration boards in an FPGA accelerator side may be avoided, thereby improving the data processing efficiency.