Distributed FPGA Routing Structure for Lower Delay and Power

Solution Overview

Problem

Traditional FPGA chips have redundancy issues leading to excessive area, high power consumption, and limited fabrication capabilities due to their fixed wiring structure, which restricts the implementation of larger devices and higher operation speeds.

Innovation Solution

The implementation of an FPGA chip with a distributed multifunctional layer structure, comprising functional units, pre-allocation managers, and programmable wiring segments, allowing for flexible data transmission directions and interconnection of multiple functional blocks on a single chip, reducing metal layers and power consumption while increasing logic gates per unit area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a fixed wiring structure is used in traditional FPGA, then connection lines between adjacent RBs are sufficient and connection structure is simple, but redundancy exceeds 50% leading to excessively large area and high power consumption

Engineering Contradiction:

Improveconnection structureVSAvoidchip area

Core Design Contradiction:

Device complexityVSArea of stationary object

Solution Approach 1:

The chip is divided into multiple functional blocks, each containing a small-scale array of RBs and LBs. This segmentation reduces the wiring complexity within each block while maintaining sufficient connectivity. The functional blocks are interconnected through a hierarchical routing system, which reduces overall redundancy compared to a fully interconnected architecture.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the chip are assigned different functional characteristics. Each functional block has optimized wiring density and interconnection patterns suited to its specific function. This local optimization reduces overall redundancy while maintaining appropriate connectivity for each functional region.

Inventive Principle:

Principle #3Local quality

2Device complexity

If a fixed wiring structure is used in traditional FPGA, then connection structure is simple, but power consumption is excessively high

Engineering Contradiction:

Improveconnection structureVSAvoidpower consumption

Core Design Contradiction:

Device complexityVSUse of energy by stationary object

Solution Approach 1:

The chip is divided into multiple functional blocks, each containing a small-scale array of RBs and LBs. This segmentation reduces the wiring complexity within each block while maintaining sufficient connectivity. The functional blocks are interconnected through a hierarchical routing system, which reduces overall redundancy compared to a fully interconnected architecture.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the chip are assigned different functional characteristics. Each functional block has optimized wiring density and interconnection patterns suited to its specific function. This local optimization reduces overall redundancy while maintaining appropriate connectivity for each functional region.

Inventive Principle:

Principle #3Local quality

3Device complexity

If traditional FPGA structure is used, then sufficient connection lines between adjacent RBs are provided, but fabrication of larger devices and higher operation speeds is limited

Engineering Contradiction:

Improveconnection structureVSAvoidoperation speed

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The chip is divided into multiple functional blocks, each containing a small-scale array of RBs and LBs. This segmentation reduces the wiring complexity within each block while maintaining sufficient connectivity. The functional blocks are interconnected through a hierarchical routing system, which reduces overall redundancy compared to a fully interconnected architecture.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a vertical dimension to the architecture by stacking multiple functional blocks in three-dimensional integration. This allows for higher operation speeds and larger device capacity without proportionally increasing wiring complexity, as vertical interconnects provide direct pathways between blocks.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11211933B2FPGA chip with distributed multifunctional layer structure

Publication Date: 2021.12.28 HERCULES MICROELECTRONICS CO LTD

AI summary

An FPGA chip includes one functional unit, one pre-allocation manager, and wiring segments. The functional unit includes a first module CPE and a second module PLF. The pre-allocation manager may be connected by means of one of the wiring segments. By configuring one pre-allocation manager, data transmission directions of the wiring segments may be changed. The functional unit is connected to one pre-allocation manager by means of a conventional line. The first module CPE and the second module PLF which are adjacent in the same functional unit are connected by means of a cross-connection line. The second functional modules are interconnected by means of a conventional routing system. Different functional blocks can be connected to each other from any position of a circuit.