Distributed Gate Driving Circuit for Display Devices
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Solution Overview
Problem
The challenge is to minimize the non-display area in display devices to enhance user experience by reducing visual boundaries between connected display panels, while maintaining efficient operation and manufacturing cost-effectiveness.
Innovation Solution
A display device design featuring a gate driving circuit with stages configured to output carry and scan signals, where the gate driving circuit is distributedly located at the display area, and includes a dummy stage to initialize and reset stages, reducing the need for additional signal lines and minimizing the non-display area by optimizing the arrangement of clock lines and power supply lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gate driving circuit is distributedly located at the display area, then the non-display area is reduced, but the device complexity increases
Solution Approach 1:
The gate driving circuit is divided into multiple stages distributed across the display area. Each stage processes a portion of the gate lines, allowing the circuit to be integrated within the display region rather than requiring a separate non-display area. This segmentation enables spatial distribution of functionality while maintaining overall system coherence.
Solution Approach 2:
The gate driving circuit stages are arranged in a two-dimensional distribution pattern across the display area rather than being concentrated in a one-dimensional non-display region. This dimensional reorganization allows the circuit to occupy display area space efficiently while maintaining signal integrity and functional performance.
2Ease of manufacture
If the gate driving circuit stages are distributedly located, then manufacturing cost is reduced, but the ease of manufacture decreases
Solution Approach 1:
The gate driving circuit is segmented into multiple identical or similar stages that can be manufactured using standardized processes. Each stage follows the same structural pattern, enabling modular manufacturing approaches that reduce overall production costs while managing complexity through repetition and standardization.
Solution Approach 2:
The distributed stage architecture allows for parameter optimization in manufacturing, such as adjusting the number of stages, their spatial arrangement, and interconnections based on specific display size and resolution requirements. This flexibility enables cost-effective manufacturing by tailoring the circuit configuration to production capabilities and display specifications.
3Area of stationary object
If clock lines are spaced with pixels interposed, then the non-display area is minimized, but the reliability of signal transmission may be affected
Solution Approach 1:
The clock signal transmission path is segmented through the pixel array, with each pixel serving as an intermediate node. This segmentation allows clock lines to be routed through the display area without requiring dedicated non-display space, while the pixel structure itself provides natural shielding and signal isolation that maintains transmission reliability.
Solution Approach 2:
Pixels act as intermediary elements between clock lines and the gate driving circuit stages. The pixel structure serves as a mediator that facilitates signal transmission through the display area while providing electrical isolation and reducing interference, thereby maintaining signal integrity despite the distributed routing configuration.
Data Source
AI summary
A display device, includes: pixels at a display area; gate lines at the display area, and connected to the pixels; carry clock lines and scan clock lines at the display area; and a gate driving circuit distributedly located at the display area, and connected to the carry clock lines, the scan clock lines, and the gate lines. The gate driving circuit includes a plurality of stages, each of the stages to output, as a carry signal, a carry clock signal supplied through a corresponding carry clock line from among the carry clock lines, and to output, as a scan signal, a scan clock signal supplied through a corresponding scan clock line from among the scan clock lines. The corresponding carry clock line and the corresponding scan clock line corresponding to one stage from among the stages are spaced from each other with at least one of the pixels interposed therebetween.