Distributed GPU Chiplet Architecture with Inter-Chiplet Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional monolithic CPU architectures face challenges in scaling down due to increased electrical resistance in contact pads and wires, which outweighs the benefits of power reduction, and chiplet design methodologies have been difficult to implement in GPU architectures due to synchronization and programming model inefficiencies.
Innovation Solution
A distributed architecture using chiplets with high-performance interconnection, where geometry and pixel workloads are processed by multiple processing units with duplicated fixed function hardware blocks and shaders, and a shared coherent cache, allowing for checkerboarding of pixel processing across units to maintain low latency and high bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the dimensions of contact pads or wires are reduced in a conventional monolithic CPU, then power consumption is reduced, but electrical resistance increases
Solution Approach 1:
The patent divides the monolithic CPU into multiple chiplets that can be independently fabricated and then interconnected. This segmentation allows each chiplet to maintain optimal contact pad and wire dimensions for low resistance while the overall system achieves power reduction through distributed architecture and selective fabrication nodes.
2Productivity
If chiplet design methodology is implemented in GPU architecture, then manufacturing efficiency and yield are improved, but synchronization and programming model inefficiencies occur
Solution Approach 1:
The patent introduces an intermediary bridge chiplet that mediates communication and synchronization between multiple GPU chiplets. This bridge chiplet handles the complex synchronization protocols and data routing, allowing individual chiplets to operate independently while maintaining coherent GPU functionality, thus resolving the synchronization inefficiencies.
Solution Approach 2:
The bridge chiplet serves multiple functions including data routing, synchronization coordination, and protocol translation between different chiplets. This multi-functional design consolidates the complexity of inter-chiplet communication into a single universal component, improving ease of operation while maintaining manufacturing efficiency.
Data Source
AI summary
An apparatus includes a command buffer configured to temporarily store commands. The apparatus also includes processing units disposed at a substrate. The processing units are configured to access a plurality of copies of a command from the command buffer. The processing units include first processing units (such as fixed function hardware blocks) to perform geometry operations indicated by the command on a set of primitives. The geometry operations are performed concurrently by the first processing units. The processing units also include second processing units (such as shaders) to process mutually exclusive sets of pixels generated by rasterizing the set of primitives. The apparatus also includes a cache to temporarily store the pixels after shading by the shaders. The processing units stop or interrupt processing commands in response to detecting a synchronization point and resume processing the commands in response to all the processing units completing commands before synchronization point.