Distributed Hardware Queue Manager for Multi-Core Inter-Communication
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Solution Overview
Problem
In multi-core processors, communication between cores becomes a limiting factor for performance scaling due to high latency and low throughput, especially in architectures with a large number of cores, as it involves significant software and hardware overhead for managing data structures and cache coherence.
Innovation Solution
The implementation of hardware queue managers with enqueue and dequeue circuitry, request buffers, scheduling circuitry, credit management, and queue migration capabilities, along with queue mapping units for virtual to physical address translation, optimizes inter-core communication by managing requests efficiently and dynamically reconfiguring queues for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If software-managed shared memory space is used for inter-core communication, then implementation simplicity is maintained, but communication latency increases and throughput decreases as number of cores increases
Solution Approach 1:
The patent replaces software-based queue management with hardware queue managers that have dedicated enqueue and dequeue circuitry. This substitution of software mechanisms with hardware circuits eliminates the need for software overhead in managing data structures and flow control, directly resolving the contradiction between implementation simplicity and communication throughput.
Solution Approach 2:
The patent divides the communication management function into separate hardware queue managers for each core, with each queue manager independently handling enqueue and dequeue operations. This segmentation allows parallel processing of communication tasks across multiple cores without software coordination overhead, improving throughput while maintaining simple per-core implementation.
2Productivity
If additional hardware components are added for queue management, then communication throughput improves, but hardware overhead and device complexity increase
Solution Approach 1:
The patent merges the queue management functionality with the existing processor core architecture by integrating hardware queue managers as part of the core infrastructure. The enqueue and dequeue circuitry are combined with the core's execution and memory management units, allowing queue operations to be handled within the existing hardware framework rather than adding separate standalone components.
Solution Approach 2:
The hardware queue managers are designed to serve multiple functions: they handle inter-core communication, manage data structure operations, control flow communication, and coordinate cache coherence. This multi-functionality reduces the need for separate dedicated hardware components for each function, thereby improving throughput without proportionally increasing hardware overhead.
3Ease of operation
If centralized queue management is used, then software control is simplified, but latency increases due to communication distance and management overhead
Solution Approach 1:
The patent segments the centralized queue management into distributed hardware queue managers, with each core having its own queue manager that handles local enqueue and dequeue operations. This segmentation places queue management closer to the data processing location, reducing communication distance and latency while maintaining simple control through local hardware automation.
Solution Approach 2:
Each hardware queue manager autonomously manages its own operations without requiring centralized software control. The enqueue and dequeue circuitry automatically handle data structure management, flow control, and coordination with other cores, eliminating latency associated with centralized management while maintaining operational simplicity through hardware self-management.
Data Source
AI summary
Technologies for a distributed hardware queue manager include a compute device having a processor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.