Distributed Landing Pads for IC Packing Density

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Solution Overview

Problem

Current IC packaging technologies limit packing density due to the need for redistribution wiring layers and peripherally located bond pads, which are resource-intensive and space-consuming.

Innovation Solution

The integration of landing pads distributed throughout one side of the IC, eliminating the need for peripheral bond pads and redistribution wiring layers, allowing for direct connection to external components via conductive lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional IC packaging with peripheral bond pads and redistribution wiring layers is used, then reliable electrical connections are achieved, but board space is increased and packing density is reduced

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidboard space
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from a one-dimensional peripheral arrangement of bond pads to a two-dimensional distributed array of landing pads across the IC surface. This dimensional change allows electrical connections to be established at multiple locations simultaneously, reducing the need for extensive redistribution wiring and minimizing board space while maintaining connection reliability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the single peripheral bond pad function into multiple distributed landing pads across the IC surface. Each landing pad serves as an independent connection point, segmenting the electrical connection function to eliminate the need for complex redistribution wiring layers and reduce overall board space requirements.

Inventive Principle:
Principle #1Segmentation

2Reliability

If peripheral bond pads and redistribution wiring layers are used, then electrical connections are established, but manufacturing complexity and costs increase

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the redistribution wiring layer from the packaging structure by directly exposing landing pads on the IC surface. This removal of the intermediate RDL layer simplifies the manufacturing process, reduces the number of fabrication steps required, and lowers production costs while maintaining reliable electrical connections.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of routing connections from peripheral bond pads through complex redistribution wiring layers, the patent inverts the approach by placing landing pads directly at the IC locations where connections are needed. This inversion eliminates the need for signal redistribution and simplifies both manufacturing and design processes.

Inventive Principle:
Principle #13The other way round (Inversion)

3Ease of manufacture

If minimum IC die size is maintained for peripheral bond pads, then bond pad space is sufficient, but packing density is limited

Engineering Contradiction:
Improvebond pad accommodationVSAvoidpacking density
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent utilizes the two-dimensional surface area of the IC die to distribute landing pads, rather than confining bond pads to the one-dimensional periphery. This allows the IC die to be reduced in size while still providing sufficient connection points, thereby increasing packing density without compromising the ability to accommodate necessary electrical connections.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8558353B2Integrated circuit having an uppermost layer comprising landing pads that are distributed thoughout one side of the integrated circuit
Publication Date: 2013.10.15 TEXAS INSTRUMENTS INC
  • US8558353B2 patent drawing
  • US8558353B2 patent drawing
  • US8558353B2 patent drawing

AI summary

An electrical device comprising an integrated circuit (IC) having an uppermost layer that includes landing pads that are distributed throughout one side of the IC.