Distributed LFSR CRC Generation for Shared Multi-Link Hardware
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Solution Overview
Problem
As computing environments evolve, the increasing complexity and size of linear feedback shift registers (LFSR) required for cyclic redundancy check (CRC) calculations consume more space and power, especially with higher bits per data word, leading to inefficiencies in data transfer reliability.
Innovation Solution
A method for generating CRC values using smaller and fewer LFSR circuits by separating CRC calculations into sub-calculations and employing programmable XOR engines with table lookups, allowing for shared LFSR circuits between link CRC and end-to-end CRC calculations, and time-multiplexing across multiple links.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LFSR circuit size is increased to handle more bits per data word, then data transmission reliability is improved, but hardware surface area consumption increases
Solution Approach 1:
The patent divides the CRC calculation into multiple independent stages, each handling a portion of the data words. Multiple LFSR circuits are configured to process different segments of data in parallel, allowing the system to maintain high reliability for multi-bit data words while keeping individual LFSR circuit sizes manageable.
Solution Approach 2:
The LFSR circuits are designed to be reconfigurable and shareable across multiple links and protocols. The same LFSR hardware can be dynamically allocated to different CRC calculation tasks, enabling a single circuit to serve multiple functions and reducing the total hardware surface area required.
2Reliability
If multiple LFSR circuits are implemented to support multiple CRC values, then data transmission reliability is improved, but power consumption increases
Solution Approach 1:
The patent merges multiple LFSR circuits into a shared resource pool that can be dynamically allocated. Instead of having dedicated LFSR circuits for each CRC value, the system combines them into a unified structure that time-multiplexes across multiple links, reducing total power consumption while maintaining the ability to compute multiple CRC values simultaneously.
Solution Approach 2:
The LFSR circuits operate in periodic time-multiplexed cycles, serving different links and protocols in sequential time slots. This periodic operation allows the same hardware to handle multiple CRC calculations over time, reducing the need for continuously powered redundant circuits and thereby lowering overall power consumption.
3Reliability
If LFSR circuit complexity is increased to handle higher bits per data word, then data transmission reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the complex CRC calculation into multiple simpler stages, where each stage processes a subset of data words. This segmentation transforms a single complex LFSR operation into multiple manageable steps, reducing the instantaneous complexity of individual circuit operations while achieving the same reliability outcome.
Solution Approach 2:
The system employs dynamic configuration of LFSR circuits, where the circuit topology and operational parameters can be adjusted based on the specific data width and protocol requirements. This dynamic adaptability allows the device to handle varying complexity requirements without being permanently configured for the maximum case, thereby reducing average device complexity.
Data Source
AI summary
Cyclic redundancy check (CRC) values are efficiently calculated using an improved linear feedback shift register (LFSR) circuit. CRC value generation is separated into two sub-calculations, which are then combined to form a final CRC value. A programmable XOR engine performs logic functions via a table lookup rather than via a random logic circuit. LCRC and ECRC calculations are performed using a single shared LFSR circuit. Multiple links share the same CRC value generator. One advantage of the present invention is that CRC values are generated using smaller and fewer LFSR circuits relative to conventional circuit designs. As a result, a CRC value generator utilizing the disclosed techniques consumes less surface area of an integrated circuit and consumes less power, resulting in cooler operation.