Distributed Lock Assemblies for Multi-Core Thread Congestion
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Solution Overview
Problem
Existing on-chip multi-core/many-core processors face challenges in implementing mutually-exclusive operations for multiple threads, leading to inefficiencies such as increased system overheads and congestion, particularly when accessing shared memory resources.
Innovation Solution
Distributing multiple lock assemblies on the chip to manage lock application and release messages, where each lock assembly handles a subset of locks, allowing for efficient calculation of the lock assembly based on the memory address, thereby reducing wait times and improving thread collaboration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a flag bit in external memory is used for lock management, then mutually-exclusive operation can be implemented, but system overheads increase and access speed decreases
Solution Approach 1:
The patent divides the monolithic synchronization management apparatus into multiple distributed lock assemblies (first lock assembly, second lock assembly, etc.). Each lock assembly independently manages a subset of locks, allowing parallel processing of lock requests from different threads. This segmentation eliminates the single-point bottleneck, reducing lock acquisition time while maintaining mutual exclusion correctness through distributed coordination.
Solution Approach 2:
The patent transitions from a centralized single-dimension lock management approach to a distributed multi-dimension architecture. Lock assemblies are distributed across different spatial locations on the chip, and threads can access different lock assemblies simultaneously. This dimensional distribution allows concurrent lock operations that would otherwise serialize through a single central apparatus, significantly reducing wait times.
2Use of energy by moving object
If a centralized synchronization management apparatus is used, then external memory access is avoided, but thread congestion increases and wait time increases
Solution Approach 1:
The centralized synchronization management apparatus is segmented into multiple distributed lock assemblies, each capable of independently handling lock requests. This segmentation distributes the processing load across multiple units, preventing congestion at any single point. Threads experiencing lock contention can be routed to different lock assemblies, maintaining high productivity while keeping all lock management operations on-chip.
Solution Approach 2:
The patent creates multiple copies of the lock assembly functionality distributed across the chip. Each lock assembly is a functional copy that can independently manage locks, eliminating the single-point bottleneck of a centralized apparatus. This copying approach maintains the energy efficiency of on-chip operations while dramatically improving throughput by allowing parallel lock management.
3Reliability
If constant polling of flag bit is performed, then lock acquisition can be detected, but on-chip network pressure increases
Solution Approach 1:
The lock assemblies provide self-service through event-driven notifications. Instead of threads continuously polling lock status, the lock assemblies automatically notify waiting threads when lock state changes occur. This self-service mechanism eliminates wasteful polling traffic on the on-chip network, reducing energy consumption while maintaining reliable lock state detection through direct notification channels.
Solution Approach 2:
The patent implements a feedback mechanism where lock assemblies actively notify threads of state changes. When a lock becomes available, the lock assembly sends a notification feedback signal to the waiting thread, eliminating the need for continuous polling. This feedback-driven approach reduces network traffic and energy consumption while ensuring threads are promptly notified of lock availability.
Data Source
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AI summary
Embodiments of the present invention provide a method, an apparatus, and a chip for implementing a mutually-exclusive operation of multiple threads, where multiple lock assemblies are distributed on a chip to separately manage a lock application message for applying for a lock and a lock release message for releasing a lock that are of different small cores, so that a congestion problem generated when a quantity of threads increases can be solved, and a speed of collaborative execution of the threads can be improved. The method includes: receiving a lock message sent by a small core, where the lock message carries a memory address corresponding to a lock requested by a first thread in the small core, and the lock message is a lock application message or a lock release message; calculating, by using the memory address of the requested lock, a code number of a lock assembly to which the requested lock belongs; and sending the lock message to the lock assembly corresponding to the code number, to request the lock assembly to process the lock message. The present invention is applicable to the field of computers.