Distributed Memory Buffer Address Sequencing
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Solution Overview
Problem
Current memory systems face bandwidth limitations in communication links, affecting performance due to the transmission of control and response signals, which impede the speed and efficiency of data access and processing in computing systems.
Innovation Solution
A distributed memory system architecture that optimizes data bandwidth by using a memory control circuit to decode commands and send write-to-buffer and store-from-buffer commands, with data tags only transmitted over control links between the memory control circuit and data buffer circuits, reducing the demand on communication links and improving data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If control and response signals are transmitted over communication links in a memory system, then memory operations can be coordinated and managed, but bandwidth limitations are imposed that reduce data transfer efficiency
Solution Approach 1:
The patent segments the communication architecture by introducing dedicated control links separate from data links. The memory system divides communication pathways into control signal channels (for commands and addresses) and data channels (for actual data transfer), allowing simultaneous independent operation without bandwidth contention.
Solution Approach 2:
The patent introduces buffer circuits as intermediary components between the memory controller and memory devices. These buffers act as mediators that receive control signals on control links and data signals on data links, then coordinate their interaction to perform memory operations without requiring control and data to share the same communication bandwidth.
2Speed
If multiple memory channels and DIMMs are controlled to meet increasing computing demands, then memory capacity and access speed are improved, but the amount of control and response signals increases, further impacting performance
Solution Approach 1:
The patent applies segmentation by creating separate control links for each memory channel or DIMM, allowing control signals to be transmitted independently on dedicated pathways rather than sharing data channels. This reduces the volume of control signals impacting any single communication link while supporting multiple high-speed memory channels.
3Productivity
If data tags and addresses are transmitted over communication links to memory devices, then data can be stored and retrieved at specific locations, but this consumes bandwidth that could be used for actual data transfer
Solution Approach 1:
The patent extracts control information (data tags and addresses) from the data communication pathway and transmits it separately over dedicated control links. This separation removes the overhead of control signal transmission from the data transfer bandwidth, allowing maximum utilization of data links for actual data movement while control links handle addressing and tagging information.
Data Source
AI summary
One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. The memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.