Distributed Memory Controller for Multi-GPU Shared Resource Access
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Solution Overview
Problem
Existing multi-GPU environments face challenges in granting controlled access to shared resources without requiring a single point of control, leading to potential data corruption and timing lags due to the need for additional chip area and latency.
Innovation Solution
Implementing a mechanism where each GPU writes to and reads from dedicated fields in a shared memory, computing a value to determine access, using a multi-summed semaphore or request/acknowledgement mechanism to ensure only one GPU accesses the shared resource at a time, eliminating the need for a single point of control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single memory controller is used to control access to shared memory in a multi-GPU environment, then controlled access is achieved, but additional chip area is required and timing lags occur
Solution Approach 1:
The patent divides the centralized memory controller functionality into distributed memory controllers at each GPU. Each GPU has its own memory controller that can independently manage access to shared memory, eliminating the need for a single centralized controller and reducing chip area requirements.
Solution Approach 2:
The patent introduces a semaphore mechanism as an intermediary that coordinates access between multiple GPUs without requiring a centralized controller. The semaphore acts as a mediator that GPUs can independently query and update to determine access rights to shared memory resources.
2Reliability
If a single memory controller is used to control access to shared memory in a multi-GPU environment, then controlled access is achieved, but timing lags occur due to stalling
Solution Approach 1:
By segmenting the memory control functionality across multiple independent controllers at each GPU, the system eliminates single points of failure and timing lags. Each GPU can independently determine access rights without waiting for a centralized controller decision.
Solution Approach 2:
Each GPU is equipped with its own memory controller that can independently manage access to shared memory. The GPUs use a semaphore mechanism to self-coordinate access without requiring intervention from a centralized controller, eliminating timing lags caused by stalling at a single control point.
3Reliability
If additional wires are added to couple GPUs to a single memory controller, then controlled access is achieved, but chip area increases
Solution Approach 1:
The patent distributes memory controller functionality to each GPU, eliminating the need for extensive wiring to a centralized controller. Each GPU independently manages its own access to shared memory through local control logic and semaphore-based coordination.
Solution Approach 2:
The semaphore mechanism serves as an intermediary that enables coordinated access between GPUs without requiring physical wiring connections to a centralized controller. The semaphore can be implemented in shared memory, reducing the need for additional physical wires and chip area.
Data Source
AI summary
Disclosed are methods and systems for granting an application-specific integrated circuit (ASIC) in a multi-ASIC environment controlled access to a shared resource. A system includes a first ASIC, a second ASIC, and a shared memory that stores a shared resource and a data set partitioned into fields. The first ASIC writes data to a first subset of the fields and reads data from the fields. The first ASIC includes first logic that computes a first value based on the data read from the fields. The second ASIC writes data to a second subset of the fields and reads data from the fields. The second ASIC includes second logic that computes a second value based on the data read from the fields. Based on the first and second values respectively computed by the first and second logic, only one of the first and second ASICs gains access to the shared resource.