Distributed Memory Controller Ring Bus Wiring Density

Solution Overview

Problem

Present memory controller systems face challenges with high wiring density and electrical noise due to the centralized layout of memory controllers in integrated circuits, which complicates layout and routing and generates heat during high memory access cycles.

Innovation Solution

A distributed memory controller system is implemented using a ring bus structure that routes request and return signals across the periphery of the integrated circuit, reducing wiring density at the center and incorporating deadlock avoidance mechanisms with virtual channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a centralized memory controller layout is used to interconnect memory devices to memory clients, then any client can access any memory device through the switch matrix, but the wiring density at the center of the chip increases geometrically and electrical noise increases during high memory access cycles

Engineering Contradiction:

Improvememory access flexibilityVSAvoidwiring density

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the monolithic centralized memory controller into multiple distributed memory controller circuits positioned at different locations on the chip. Each distributed controller handles a subset of memory devices and clients, dividing the interconnection burden and reducing wiring density at any single location while maintaining system-wide connectivity and access flexibility.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from a two-dimensional centralized switch matrix to a multi-dimensional distributed architecture where memory controllers are positioned at multiple locations throughout the chip. This spatial distribution across different dimensions reduces the concentration of wiring at the center while maintaining connectivity through coordinated operation of multiple controllers.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If a centralized memory controller layout is used to interconnect memory devices to memory clients, then any client can access any memory device through the switch matrix, but the layout and routing become difficult due to high wire density

Engineering Contradiction:

Improvememory access flexibilityVSAvoidlayout and routing difficulty

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent segments the monolithic centralized memory controller into multiple distributed memory controller circuits positioned at different locations on the chip. Each distributed controller handles a subset of memory devices and clients, dividing the interconnection burden and reducing wiring density at any single location while maintaining system-wide connectivity and access flexibility.

Inventive Principle:

Principle #1Segmentation

3Productivity

If a centralized memory controller layout is used to interconnect memory devices to memory clients, then memory data can be accessed through a unified circuit, but heat generation increases during periods of increased memory access cycles

Engineering Contradiction:

Improvememory access efficiencyVSAvoidheat generation

Core Design Contradiction:

ProductivityVSTemperature

Solution Approach 1:

The patent segments the monolithic centralized memory controller into multiple distributed memory controller circuits positioned at different locations on the chip. Each distributed controller handles a subset of memory devices and clients, dividing the interconnection burden and reducing wiring density at any single location while maintaining system-wide connectivity and access flexibility.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements local memory controller circuits positioned near specific memory devices and clients, allowing local access operations to be handled locally without traversing the entire chip. This reduces heat generation in any single region while maintaining overall memory access efficiency through coordinated operation of multiple local controllers.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS7849256B2Memory controller with ring bus for interconnecting memory clients to memory devices

Publication Date: 2010.12.07 ATI TECHNOLOGIES ULC

AI summary

Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller.