Distributed Multi-PLL Loop Filters for Phase Noise and LO Power
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Solution Overview
Problem
Existing wireless communication networks face challenges in achieving low phase noise and efficient power consumption in distributed Phase Locked Loops (PLLs) used for Local Oscillator (LO) signal generation, particularly in highly parallel architectures with multiple antennas.
Innovation Solution
A distributed multi-PLL system is implemented across an Integrated Circuit (IC), where a common reference signal is distributed to all PLLs. Each PLL has two loop filters: a common mode loop with low bandwidth for reference noise control and a difference mode loop with high bandwidth to suppress phase differences between PLL outputs, effectively acting as a single PLL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single high-performance PLL is used to provide LO signals to all transceivers, then phase noise performance is improved, but power consumption increases and routing challenges arise
Solution Approach 1:
The patent divides the single high-performance PLL into multiple distributed PLLs, each serving a subset of transceivers. This segmentation reduces the power consumption and routing complexity of individual PLLs while maintaining overall system performance through synchronized operation and phase alignment mechanisms.
2Use of energy by moving object
If multiple distributed PLLs are used to reduce power consumption, then power efficiency improves, but phase noise performance deteriorates
Solution Approach 1:
The patent implements feedback mechanisms where each distributed PLL monitors its phase error relative to a reference signal and adjusts its operation accordingly. This feedback control enables multiple low-power PLLs to maintain phase noise performance comparable to a single high-performance PLL by continuously correcting phase deviations.
3Adaptability or versatility
If multiple distributed PLLs are deployed, then modularity and ease of configuration improve, but phase coherence between PLLs becomes difficult to maintain
Solution Approach 1:
The patent creates an equipotential phase reference environment by distributing a common reference signal to all distributed PLLs and implementing phase alignment mechanisms. This ensures that all PLLs operate at the same phase potential relative to the reference, maintaining phase coherence across the modular system while allowing flexible configuration and scalability.
Data Source
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AI summary
A plurality of Phase Locked Loops, PLL (12, 14), are distributed across an Integrated Circuit, each receiving a common reference signal (A). A local phase error (B) of each PLL (12, 14) is connected to a phase error averaging circuit (16), which calculates an average phase error (C), and distributes it back to each PLL (12, 14). In each PLL (12, 14), two loop filters (20, 22) with different bandwidths are deployed. A lower bandwidth, high DC gain, common mode loop operates on the average phase error, and forces the PLL outputs (H) to track the phase of the common reference signal. A high bandwidth, difference mode loop operates on the difference between the local phase error (B) and the average phase error (C) to suppress phase differences between PLL outputs, minimizing interaction between them. The reference noise contribution at the output is controlled by the common mode loop, which can have a low bandwidth. The reference noise contribution and oscillator interaction suppression are thus independently controlled.