Distributed Multi-Bus Queues for Asynchronous Multi-CPU Data Routing
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Solution Overview
Problem
As chip density increases, synchronizing reliable data transfers based on a single clock becomes increasingly difficult, leading to poor performance and user experience.
Innovation Solution
Implementing a distributed queue multi-bus (DQMB) architecture on multi-CPU chips, utilizing multiple buses in pairs for upstream and downstream communication, with a grid layout and asynchronous operation, and employing Bellman-Ford shortest path routing and time division multiplexing to optimize data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If chip density increases, then more transistors can be used on chips, but synchronizing reliable data transfers based on a single clock becomes increasingly difficult
Solution Approach 1:
The patent divides the single clock system into multiple independent clock domains, with each CPU core having its own clock. This segmentation allows each component to operate independently without synchronization issues, resolving the contradiction between high density and reliable data transfer.
Solution Approach 2:
The patent introduces a message passing interface (MPI) as an intermediary layer between CPU cores. This MPI handles data transfer coordination and synchronization, allowing reliable communication between independently clocked cores without requiring a global clock signal.
2Volume of moving object
If chip density increases, then hardware becomes smaller, but synchronizing reliable data transfers based on a single clock becomes increasingly difficult
Solution Approach 1:
The patent segments the chip into multiple independent processing units, each with its own clock domain. This allows small chip size while maintaining reliable data transfer through localized synchronization within each segment rather than requiring global clock distribution across the entire chip.
Solution Approach 2:
The patent transitions from a single-dimension global clock synchronization approach to a multi-dimensional approach where each CPU core operates in its own clock domain. Data transfer reliability is achieved through message passing protocols that operate across these dimensional boundaries rather than through temporal synchronization.
3Device complexity
If a single clock is used for data transfers, then synchronization is simpler, but chip performance suffers and user experience is poor
Solution Approach 1:
The patent segments the clocking architecture into multiple independent domains, one for each CPU core. This reduces the complexity of global clock distribution and synchronization while enabling higher performance through parallel operation of multiple cores without clock contention.
Solution Approach 2:
Each CPU core independently manages its own clock domain and data transfer operations through the message passing interface. This self-service approach eliminates the need for complex centralized clock synchronization while maximizing chip performance through autonomous parallel processing.
Data Source
AI summary
Distributed queue multi-bus on multi-CPU chips is enabled. For example, a method can comprise generating, by a system comprising a processor, a reservation request for a bus between a source node and a destination node, based on the reservation request, adding, by the system, data applicable to the reservation request to a queue of a bus located between the source node and the destination node, using a defined data routing process, determining, by the system, a path between the source node and the destination node, and in response to the queue being determined to comprise no other reservation requests prior to the reservation request, sending, by the system, data from the source node to the destination node via the bus.