Multi-layer Distributed Network for IC Test Signal Routing
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Solution Overview
Problem
Integrated circuit devices face routing congestion during intensive test signal routing, especially in complex designs, due to increased test signals and varying resource usage, which complicates the distribution of signals and can lead to timing issues and resource allocation challenges.
Innovation Solution
A two-layer signal distribution network is implemented, with a pre-defined, non-customizable base layer providing a structured test signal network that spans across the device, branching into quadrants and connecting to logic elements through a customizable layer, allowing efficient test signal routing without congesting the custom layer, and incorporating buffers to ensure deterministic timing and reduce current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If test signals are routed through the customizable layer, then routing flexibility is improved, but routing congestion increases
Solution Approach 1:
The patent divides the routing function into two segments: a pre-built network layer for high-fanout test signals and a customizable layer for design-specific routing. This segmentation allows test signal routing to be separated from custom logic routing, reducing congestion in the customizable layer while maintaining routing flexibility for both purposes.
Solution Approach 2:
The patent introduces a vertical dimension by stacking two routing layers, one pre-built and one customizable. This multi-layer approach allows test signals to utilize the pre-built network infrastructure without competing for routing resources in the customizable layer, effectively adding a new dimension to the routing architecture.
2Device complexity
If a pre-built network is implemented, then routing congestion is reduced, but timing determinism may be compromised
Solution Approach 1:
The patent applies different routing qualities to different signal types: the pre-built network provides optimized, deterministic paths for high-fanout test signals, while the customizable layer provides flexible routing for design-specific signals. This local quality differentiation ensures timing determinism where needed without sacrificing overall routing flexibility.
Solution Approach 2:
The pre-built network is designed to serve multiple functions: it provides deterministic timing for test signals while also being compatible with the customizable layer for design-specific routing. This multi-functionality allows the same architecture to satisfy both timing determinism requirements and routing flexibility needs.
3Reliability
If more test pins are added, then test coverage is improved, but routing area increases
Solution Approach 1:
The patent merges the test signal routing infrastructure with the device's existing multi-layer architecture. By integrating the pre-built test network into the same physical substrate as the customizable logic layers, the design achieves enhanced test coverage without proportionally increasing the overall device area, as both functions share the same physical space.
Data Source
AI summary
Apparatuses and processes for distributing signals in an integrated circuit are disclosed. An embodiment to use a custom layer together with a base layer on an integrated circuit for testing the integrated circuit includes having a structured network on the base layer. The custom layer connects the network to logic elements on the integrated circuit. The network may be evenly distributed across the base layer of the integrated circuit. Even distribution of the network may reduce skew of the test signals. Buffers are also placed along the structured network. The buffers may be placed to ensure a deterministic test signals distribution. Unused buffers in the base layer may be tied off to reduce current leakage.