Distributed Network Switch Scaling via Virtual Core Interfaces
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Network processors and switching ASICs with tightly coupled switching and packet processing cores have fixed bandwidth, making it impossible to dynamically increase switching and packet processing bandwidth by adding more elements.
Innovation Solution
A system with multiple central core processing devices and packet processors that use virtual central core interfaces and packet processor interface managers to establish scaled-out and distributed connectivity, allowing dynamic addition of packet processors based on bandwidth demand.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If tightly coupled switching and packet processing cores are used on the same physical ASIC, then integration and coordination are improved, but bandwidth scalability deteriorates
Solution Approach 1:
The system segments the network processing architecture into separate central core processing devices and packet processor entities. Each packet processor can be independently added or removed from the system, allowing bandwidth scalability while maintaining stable core processing functions. The segmentation enables the system to grow dynamically by adding packet processors without requiring changes to the core processing architecture.
Solution Approach 2:
The patent introduces a new dimension of virtualization with virtual central core interfaces, transforming the traditional single-physical-ASIC architecture into a multi-device distributed system. This dimensional change allows multiple packet processors to connect to multiple central core processing devices through virtual interfaces, enabling scalable bandwidth expansion while maintaining architectural stability.
2Device complexity
If fixed switching and packet processing ASICs are used, then system simplicity is improved, but dynamic bandwidth addition capability deteriorates
Solution Approach 1:
The system implements dynamic packet processor addition capability where packet processors can be added or removed based on bandwidth demand. The architecture supports dynamic reconfiguration of packet processor connections to central core processing devices, allowing the system to adapt to changing network requirements without complete system redesign.
Solution Approach 2:
The central core processing devices and packet processors are designed with universal interfaces and protocols that allow any packet processor to connect to any central core processing device. This universality enables flexible dynamic addition of bandwidth capacity while maintaining relatively simple individual component designs.
3Adaptability or versatility
If distributed and scaled-out packet processing is implemented, then bandwidth scalability is improved, but system complexity deteriorates
Solution Approach 1:
The system uses virtual central core interfaces that create virtual copies of core processing capabilities across multiple physical devices. This copying approach allows distributed packet processing while abstracting the complexity, as packet processors interact with standardized virtual interfaces rather than dealing with the underlying distributed system complexity.
Solution Approach 2:
The virtual central core interface acts as an intermediary layer between packet processors and physical central core processing devices. This intermediary abstracts the distributed system complexity, allowing packet processors to be added and managed without directly managing the complexity of inter-device communication and coordination.
Data Source
AI summary
Embodiments of the invention relate to scaled-out and distributed network packet processors and switch central cores. One embodiment relates to a system including multiple central core processing devices, wherein each central core processing device includes: a virtual central core interface for establishing scaled-out and distributed virtual communication connections with the central core processing devices and a packet processor interface manager connected with multiple packet processing interfaces. Multiple packet processors each include: a packet processor thread manager for managing and processing packets received by central core processing devices and multiple central core processing interfaces for providing connectivity between the packet processors and the plurality of central core processing devices. The packet processing interfaces and the central core processing interfaces provide scaled-out and distributed connectivity of the packet processors to one or more central core processing devices.


