Distributed Neural Network Processing via Hamiltonian Cycles
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Solution Overview
Problem
The high computational demands and extensive data communication requirements of large neural networks become prohibitively expensive and energy-intensive due to the massive number of connections, making it challenging to efficiently process and train these networks across many processors.
Innovation Solution
Implementing a distributed processing architecture that utilizes topology to combine sequences of processors and network switches, allowing for various forms of parallelism such as data, pipeline, and layer parallelism, and configuring processors to form Hamiltonian cycles to optimize communication patterns and reduce bandwidth requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If computations for large neural networks are partitioned across many processors, then computational capacity is improved, but communication requirements and cost increase prohibitively
Solution Approach 1:
The patent divides the neural network computation into distinct segments or stages that can be processed sequentially across different processor groups. By segmenting the computation workflow rather than distributing all computations simultaneously, the system reduces the communication overhead while maintaining parallel processing benefits across multiple processors.
2Speed
If full bandwidth is provided for arbitrary communication patterns between processors, then communication performance is improved, but cost and energy consumption increase prohibitively
Solution Approach 1:
The patent implements communication optimization by establishing fixed communication patterns within processor groups where adjacent processors communicate primarily with their neighbors. This local quality approach ensures that communication bandwidth is provided only where needed for specific computation stages, rather than providing full bandwidth for all possible communication patterns, thereby reducing energy consumption while maintaining necessary communication performance.
Data Source
AI summary
Embodiments of the present disclosure include techniques for processing neural networks. Various forms of parallelism may be implemented using topology that combines sequences of processors. In one embodiment, the present disclosure includes a computer system comprising a plurality of processor groups, the processor groups each comprising a plurality of processors. A plurality of network switches are coupled to subsets of the plurality of processor groups. A subset of the processors in the processor groups may be configurable to form sequences, and the network switches are configurable to form at least one sequence across one or more of the plurality of processor groups to perform neural network computations. Various alternative configurations for creating Hamiltonian cycles are disclosed to support data parallelism, pipeline parallelism, layer parallelism, or combinations thereof.