Distributed Packet Buffering in Routers via Segmentation
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Solution Overview
Problem
Conventional routers face challenges in meeting the increasing buffer capacity requirements due to rising internet traffic, particularly with the emergence of high-bandwidth applications like 4K/8K videos and virtual/augmented reality, as existing memory technologies struggle to accommodate the necessary buffer sizes for high-speed line cards.
Innovation Solution
A packet processing method and router architecture that implement distributed packet buffering by dynamically allocating packets to available buffer blocks across multiple buffer modules, allowing for flexible and scalable buffering through the use of buffer information blocks and switching modules to manage packet allocation and scheduling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a router uses a single buffer module with capacity B*RTT to handle line card bandwidth B, then the buffer can accommodate typical traffic patterns, but the buffer capacity becomes insufficient when traffic increases to higher bandwidth requirements (e.g., 10 Tbps requiring 250 GB buffer)
Solution Approach 1:
The patent divides a single large buffer module into multiple smaller buffer blocks (first buffer blocks and second buffer blocks) distributed across different locations. Each buffer block can be independently managed and allocated, allowing the system to achieve large total capacity while maintaining manageable complexity through modular organization.
Solution Approach 2:
The patent introduces a new dimension of organization by creating buffer information blocks that map logical packet queues to physical buffer blocks across multiple buffer modules. This virtualization layer allows flexible allocation and management of buffer resources without directly managing the complexity of individual buffer blocks.
2Quantity of substance
If the router extends the buffer module to meet increasing buffer requirements, then buffer capacity increases, but it becomes difficult to determine which buffer module should receive buffered packets when multiple switching modules are present
Solution Approach 1:
The patent introduces buffer information blocks as an intermediary data structure that sits between the packet processing logic and the physical buffer blocks. These information blocks contain mapping relationships that guide packet allocation decisions, simplifying the management complexity by providing a virtualization layer that abstracts the underlying buffer distribution architecture.
3Quantity of substance
If memory technology is used to meet buffer requirements for high bandwidth line cards (e.g., 250 GB for 10 Tbps), then buffer capacity can be achieved, but existing memory technology cannot meet this requirement in the short term
Solution Approach 1:
By segmenting the buffer into multiple smaller buffer blocks distributed across available memory resources, the system can utilize existing memory technology capacity in a distributed manner. This allows the router to achieve effective large buffer capacity by aggregating multiple smaller memory units rather than relying on a single large memory component that may not be available.
Data Source
AI summary
Embodiments of the application describe a packet processing method and a router. The method includes: receiving, by an input line card, at least one packet; obtaining, by the input line card, information about an available first buffer block in a third buffer module, where the third buffer module is a first buffer module that includes an available first buffer block; allocating, by the input line card, a third buffer block to each of the at least one packet based on at least one buffer information block stored in the input line card and the information about an available first buffer block; and buffering, by the input line card, each packet into the third buffer block. Distributed packet buffering can be implemented by using the method.