Distributed Page Buffer Circuit Layout for Nonvolatile Memory Integration
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Solution Overview
Problem
As nonvolatile memory devices with increasing integration density face challenges in securing sufficient area for peripheral circuits due to expanding cell regions, existing designs struggle to efficiently utilize space for page buffer circuits and control circuits below the cell region.
Innovation Solution
A nonvolatile memory device structure is implemented with a distributed page buffer circuit and corresponding control circuit units arranged in a zigzag pattern below the cell array, allowing for efficient use of space and improved integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are formed in a single layer on a semiconductor substrate to increase integration density, then the degree of integration increases, but the area available for peripheral circuits decreases
Solution Approach 1:
The patent transitions from a two-dimensional layout where peripheral circuits are placed beside the cell array to a three-dimensional arrangement by positioning page buffer units beneath the cell array. This vertical stacking allows the cell array to occupy the upper layer while page buffer units occupy the lower layer, effectively utilizing the z-dimension to resolve the area conflict between cell region and peripheral circuit region.
Solution Approach 2:
The page buffer circuit is divided into multiple page buffer units, each corresponding to a specific region of the cell array. These segmented units are distributed beneath their respective cell regions, allowing for localized placement and more flexible space utilization. The segmentation enables the peripheral circuit area to be distributed rather than concentrated, improving overall integration density.
2Area of stationary object
If page buffer units are disposed below a cell array in a distributed fashion, then space utilization improves, but circuit layout complexity increases
Solution Approach 1:
The patent employs an asymmetric layout where page buffer units are positioned at specific locations beneath the cell array rather than in a symmetric or uniform pattern. Each page buffer unit is strategically placed to correspond to its associated cell region, creating an asymmetric but functionally optimized arrangement that maximizes space utilization while managing complexity through functional correspondence.
Solution Approach 2:
The patent introduces bit line contact holes as intermediary structures that connect the upper cell array region to the lower page buffer units. These contact holes serve as mediators that simplify the connection architecture, reducing the complexity of direct three-dimensional interconnections while enabling effective coupling between the cell array and distributed page buffer units.
Data Source
AI summary
A nonvolatile memory device includes a cell array, a distributed page buffer including a plurality of page buffer units disposed below the cell array, the plurality of page buffer units having a certain size; and a distributed page buffer control circuit including a plurality of page buffer control circuit units, each page buffer control circuit unit being arranged at one side of a corresponding page buffer unit, and configured to control operations of the corresponding page buffer unit, the plurality of page buffer control circuit units each having a predetermined size.