Distributed Phased Array Subarrays for Balanced Beam Processing
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Solution Overview
Problem
Phased array systems face issues such as load imbalance, heavy traffic load, limited scalability, and a critical single point of failure due to hierarchical architectures as the number of antennas increases, leading to operational anomalies.
Innovation Solution
Implementing a distributed processing architecture that distributes metric calculations across multiple subarray units, preprocesses metrics, and utilizes a distributed data link system to maintain balanced load distribution and scalability, while allowing for selective configuration of subarray units as control or processing units to handle failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a hierarchical architecture is used in phased array systems, then the system can be structured with clear control and processing levels, but the load becomes unbalanced and traffic load increases as the number of antennas increases
Solution Approach 1:
The system divides the phased array into multiple subarray units, each with its own processing circuit. Each subarray unit independently calculates subarray responses for multiple candidate directions, segmenting the overall processing load and preventing the bottleneck effect of centralized hierarchical architectures.
Solution Approach 2:
The patent introduces a distributed processing dimension by allowing subarray units to simultaneously perform both local processing and contribute to global metric calculations. This multi-dimensional processing approach distributes traffic load across multiple pathways rather than concentrating it through a single hierarchical chain.
2Quantity of substance
If the number of antennas increases in hierarchical phased array systems, then the system coverage and capability improve, but scalability is limited due to operational anomalies
Solution Approach 1:
By dividing the large phased array into smaller subarray units with identical or similar processing capabilities, the system can scale by simply adding more subarray units without redesigning the overall processing architecture. Each subarray unit maintains consistent functionality regardless of system size.
Solution Approach 2:
Each subarray unit is designed with universal processing capabilities to calculate responses for multiple candidate directions and perform metric calculations. This multi-functionality allows any subarray unit to be added to the system without requiring specialized processing paths, enhancing scalability.
3Device complexity
If hierarchical architecture is used, then the system has defined control structures, but single point of failure becomes critical leading to operational anomalies
Solution Approach 1:
The control structure is segmented across multiple subarray units rather than concentrated in a single controller. Each subarray unit has its own processing circuit that can independently perform metric calculations, eliminating the single point of failure inherent in centralized hierarchical control.
Solution Approach 2:
Each subarray unit possesses localized processing capabilities to perform metric calculations independently. This local quality ensures that if one subarray unit fails, others continue to operate and contribute to the overall system function, improving reliability.
4Productivity
If distributed processing is implemented across multiple subarray units, then load balance and scalability improve, but system complexity increases
Solution Approach 1:
The patent employs homogeneous subarray units with identical or similar processing circuits that perform the same set of operations. This homogeneity simplifies the distributed architecture by making all units interchangeable and easier to manage, offsetting the complexity of distribution through uniformity.
Data Source
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AI summary
A phased array system includes a plurality of subarray units. Each of the subarray units includes a set of antennas and a processing circuit. The set of antennas is arranged to couple an input signal incident on the phased array system into a set of electrical signals. The processing circuit, coupled to the set of antennas, is configured to calculate N subarray responses for N candidate directions according to the set of electrical signals and N steering vectors associated with the N candidate directions. The processing circuit of a first subarray unit included in the subarray units is further configured to generate N combined responses for the N candidate directions by combining subarray responses from the subarray units for each candidate direction, and determine directional information of the input signal according to the N combined responses.