Distributed Pin Map Memory for High-Speed NAND Testing

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Solution Overview

Problem

The increasing demand for high-speed NAND flash memory testing requires a test system that can reduce test costs and time, as existing solutions struggle to scale with the growing speed and capacity of NAND devices.

Innovation Solution

A distributed pin mapping architecture is implemented in a testing device, where pin map memory is distributed across multiple bridge components, allowing CPUs to access resources efficiently and perform operations in parallel, eliminating bottlenecks and supporting flexible combined resource modes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a centralized pin map memory architecture is used, then system simplicity is maintained, but test speed and throughput are limited due to access bottlenecks

Engineering Contradiction:

Improvetest speedVSAvoidmemory architecture complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The pin map memory is divided into multiple distributed instances located at different bridge components throughout the system. Each CPU can access local pin map data through its associated bridge without contending for a single centralized memory resource, thereby eliminating access bottlenecks and enabling high-speed parallel testing operations.

Inventive Principle:

Principle #1Segmentation

2Productivity

If multiple CPUs access a single pin map memory, then resource sharing is achieved, but access conflicts and bottlenecks increase

Engineering Contradiction:

Improvetesting throughputVSAvoidaccess time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The pin map memory resource is segmented into multiple distributed instances across different bridge components. This segmentation allows multiple CPUs to simultaneously access different pin map memory instances without conflict, thereby increasing testing throughput while minimizing access time delays.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system transitions from a single-dimension centralized memory access model to a multi-dimensional distributed access model. CPUs can access pin map data through multiple parallel paths via different bridge components, effectively adding spatial dimensions to the access topology and eliminating sequential access bottlenecks.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If test system resources are fixed, then system stability is maintained, but flexibility in supporting different testing configurations is reduced

Engineering Contradiction:

Improveconfiguration flexibilityVSAvoidsystem stability

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The distributed pin map memory architecture provides a universal resource that can be dynamically allocated and configured to support various testing scenarios. Multiple CPUs and bridge components can be configured in different combinations, allowing the system to adapt to diverse testing requirements while maintaining stable, predictable access patterns through the distributed memory structure.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS9239768B2Distributed pin map memory

Publication Date: 2016.01.19 ADVANTEST CORP

AI summary

In a testing device, a method for implementing distributed pin mapping. The method includes receiving a request from a plurality of CPUs to access a pin map memory at each of a plurality of bridges, implementing accesses to the pin map memories locally at each of the plurality of bridges, and using pin map data from the accesses to the plurality of CPUs to enable access to testing device resources.