Distributed PLL Clock Generation for Low-Jitter DDR DRAM
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Solution Overview
Problem
Current clock signal generation circuits in DDR DRAM face challenges with long clock trees introducing additional jitter and difficulty in achieving fast dynamic frequency adjustment for arbitrary frequencies.
Innovation Solution
A clock signal generation circuit comprising a global PLL and multiple local PLLs, where the global PLL generates a synchronization clock signal that is used by local PLLs to produce multiple clock signals with independent phase adjustments, reducing clock tree length and enabling fast frequency switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single PLL is used to generate all clock signals through a long clock tree, then the circuit structure is simple, but additional clock jitters are introduced and cannot be filtered
Solution Approach 1:
The patent divides the single PLL into multiple local PLLs distributed throughout the circuit. Each local PLL independently generates clock signals for its specific region, segmenting the monolithic clock generation system. This segmentation shortens individual clock tree lengths and allows each local PLL to filter jitters independently, resolving the contradiction between structural simplicity and jitter reduction.
Solution Approach 2:
The patent introduces a synchronization mechanism as an intermediary between local PLLs to coordinate their operations. This intermediary ensures that while local PLLs operate independently to reduce jitter, they remain synchronized to maintain overall system coherence, thus resolving the contradiction without sacrificing reliability.
2Stability of the object's composition
If the PLL bandwidth is kept narrow to ensure stability, then the system is stable, but fast dynamic frequency adjustment cannot be achieved
Solution Approach 1:
The patent segments the frequency adjustment function by introducing separate frequency control mechanisms for each local PLL. This allows individual frequency adjustments without destabilizing the entire system, enabling faster dynamic frequency changes while maintaining overall stability through distributed control architecture.
Solution Approach 2:
The patent implements dynamic frequency adjustment capabilities in each local PLL independently, allowing the system to adapt frequencies rapidly according to local requirements. This dynamic approach enables fast frequency switching while the synchronization mechanism maintains overall system stability, resolving the contradiction between stability and speed.
3Reliability
If multiple local PLLs are used to generate clock signals independently, then clock jitter is reduced and fast frequency adjustment is enabled, but the circuit complexity increases
Solution Approach 1:
The patent segments the clock generation function into distributed local PLLs, each handling a specific region. While this increases component count, it dramatically improves clock signal quality by shortening clock trees and enabling independent jitter filtering. The modular segmented architecture makes the complexity manageable and justifiable by the significant quality improvements.
Solution Approach 2:
The patent designs local PLLs with multi-functional capabilities, including frequency adjustment, phase synchronization, and jitter filtering in a single integrated unit. This universality reduces the need for separate dedicated circuits for each function, thereby limiting the increase in overall circuit complexity while achieving multiple performance improvements simultaneously.
Data Source
AI summary
The present invention provides a clock signal generation circuit including a global PLL and a plurality of local PLLs. In the operation of the clock signal generation circuit, the global PLL is configured to receives a reference clock signal to generate a synchronization clock signal, and the plurality of local PLLs receive the synchronization clock signal to generate a plurality of clock signals, respectively, and the plurality of clock signals are used to generate a plurality of output clock signals.