Distributed PLL Loop Filters for Phase Noise and Coupling Control
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Solution Overview
Problem
In wireless communication networks, achieving low phase noise with distributed Phase Locked Loops (PLLs) while minimizing power consumption and maintaining system performance is challenging, especially in highly parallel architectures with multiple antennas, where interactions between PLLs can lead to undesired effects.
Innovation Solution
A distributed PLL system where a common reference signal is used across multiple PLLs, with a phase error averaging circuit calculating an average phase error and distributing it back to each PLL, employing both common mode and difference mode loop filters to suppress interactions and improve phase noise performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If multiple distributed PLLs are used in highly parallel architectures, then power consumption and chip area are reduced, but phase noise performance deteriorates due to interactions between PLLs
Solution Approach 1:
The patent implements a feedback mechanism where phase error signals from multiple PLLs are collected, averaged, and fed back to all PLLs through a common mode loop filter. This feedback system enables the PLLs to coordinate their operation and suppress mutual interactions, thereby maintaining low phase noise performance while allowing multiple distributed PLLs to operate simultaneously with reduced power consumption and chip area.
Solution Approach 2:
The patent combines the phase error signals from multiple independent PLLs into a single averaged error signal that is distributed back to all PLLs. By merging the control loops through the common mode loop filter and phase error averaging circuit, the system achieves coordinated operation of multiple PLLs, suppressing harmful interactions while maintaining the benefits of distributed architecture.
2Reliability
If a single high-performance PLL is used, then phase noise performance is improved, but power consumption and chip area increase
Solution Approach 1:
The patent segments a single high-performance PLL into multiple distributed PLLs that can operate in parallel. Each PLL is simpler and consumes less power individually, but they are connected through a feedback mechanism that averages their phase errors and distributes the common mode control signal back to all PLLs. This segmentation allows the system to achieve comparable phase noise performance to a single PLL while reducing total power consumption and chip area.
3Device complexity
If multiple PLLs operate independently, then design complexity is reduced, but phase coherence between LO signals deteriorates
Solution Approach 1:
The patent introduces a feedback mechanism where phase error signals from all PLLs are averaged and distributed back to each PLL through the common mode loop filter. This feedback ensures that all PLLs maintain phase coherence with each other and with the reference signal, while still allowing each PLL to operate with relatively simple independent local oscillator and phase detector circuits.
Solution Approach 2:
The patent implements a universal common mode loop filter and phase error averaging circuit that serves all multiple PLLs simultaneously. This shared control infrastructure provides phase coherence across all PLLs while maintaining modular design where each PLL can be independently configured for its specific frequency and application requirements.
Data Source
AI summary
A plurality of Phase Locked Loops, PLL (12, 14), are distributed across an Integrated Circuit, each receiving a common reference signal (A). A local phase error (B) of each PLL (12, 14) is connected to a phase error averaging circuit (16), which calculates an average phase error (C), and distributes it back to each PLL (12, 14). In each PLL (12, 14), two loop filters (20, 22) with different bandwidths are deployed. A lower bandwidth, high DC gain, common mode loop operates on the average phase error, and forces the PLL outputs (H) to track the phase of the common reference signal. A high bandwidth, difference mode loop operates on the difference between the local phase error (B) and the average phase error (C) to suppress phase differences between PLL outputs, minimizing interaction between them. The reference noise contribution at the output is controlled by the common mode loop, which can have a low bandwidth. The reference noise contribution and oscillator interaction suppression are thus independently controlled.