Distributed Processing Circuitry Buffer Interface for Multicore Task Scheduling
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Solution Overview
Problem
Multicore computational systems face complexities in efficiently partitioning and scheduling tasks, managing shared resources, and handling inter-processing circuitry communication when executing distributed applications, leading to challenges in optimizing performance and energy efficiency.
Innovation Solution
A computational system model is developed that includes a plurality of processing circuitries, physical memory, and interconnects, with a processor type comprising a processing circuitry identifier, memory identifier, and interface identifier, enabling efficient distributed computation by abstracting the system and providing a generic programming model and API for task communication and synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If distributed applications are executed on multicore systems with task partitioning and scheduling, then productivity and throughput are improved, but device complexity increases due to task management and inter-processing-circuitry communication overhead
Solution Approach 1:
The patent introduces a buffer as an intermediary component between processing circuitries to handle data exchange. The buffer decouples the communication between processors, allowing independent task execution while maintaining data flow. This mediator approach reduces the complexity of direct inter-processing-circuitry communication while preserving productivity benefits.
Solution Approach 2:
The patent segments the computational system into independent processing circuitries that can execute tasks autonomously. Each processing circuitry operates as a separate entity with its own task queue and buffer access, enabling parallel execution without centralized coordination overhead. This segmentation reduces task management complexity while maintaining high throughput.
2Productivity
If multiple processing circuitries are integrated into a single system to handle concurrent tasks, then productivity increases through parallel execution, but ease of operation decreases due to challenges in resource management and communication handling
Solution Approach 1:
The patent implements a universal buffer interface that can be accessed by multiple processing circuitries using the same set of rules and protocols. This universal approach to inter-circuitry communication simplifies the operation complexity while enabling concurrent task execution across multiple processors.
Solution Approach 2:
Each processing circuitry independently manages its own task queue and buffer access operations without requiring centralized control. The circuits autonomously handle resource management and communication protocols, reducing the operational complexity for system users while maintaining high productivity through parallel execution.
3Ease of operation
If centralized control processors are used to manage task scheduling and communication, then ease of operation is improved through centralized coordination, but device complexity increases and productivity decreases due to bottlenecks
Solution Approach 1:
The patent extracts the centralized control function from the system architecture and replaces it with distributed autonomous processing. Each processing circuitry independently manages its tasks and communications, eliminating the centralized bottleneck while maintaining operational simplicity through standardized buffer interfaces.
Solution Approach 2:
The system transitions from static centralized control to dynamic distributed coordination. Processing circuitries dynamically adjust their task execution and buffer access based on real-time system state, enabling high throughput while maintaining operational ease through adaptive autonomous decision-making at each processing node.
Data Source
AI summary
It is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to: Control a processing circuitry of a computational system including a plurality of processing circuitries to determine if a number of input data token or tokens is available at one or more input buffers of a memory space; and control the processing circuitry to determine if at least a portion of the memory space for a number of output data token or tokens is available at one or more output buffers assigned to the processing circuitry; and control the processing circuitry to execute an iteration of a first task of an application, the application being modelled by a model, if it is determined that the number of input data token or tokens and memory space for the number of output data token or tokens are available.