Distributed Processor Testing Module for Semiconductor Reliability
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Solution Overview
Problem
Conventional semiconductor package reliability testing equipment faces performance bottlenecks due to high computational loads, leading to slow data processing speeds and increased manufacturing costs, with single component failures causing operational delays and cost inefficiencies.
Innovation Solution
The testing equipment incorporates a processor on a circuit board within each testing module, enabling local data processing and reducing the computational load on the host computer, while minimizing the number of transmission ports and allowing modular design to decrease manufacturing costs and maintain operation even with module failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single computer processes all test data from multiple semiconductor packages, then the testing system can be simplified in structure, but the data processing speed becomes extremely slow due to high computational load
Solution Approach 1:
The patent divides the centralized computer processing system into distributed processing units. Each testing socket is equipped with its own control chip that can independently process test data for semiconductor packages. This segmentation of processing functions across multiple independent units enables parallel data processing, significantly improving data processing speed while maintaining system simplicity through modular architecture
2Quantity of substance
If multiple transmission ports are configured on each circuit board to handle big data, then the data transmission capacity is improved, but the manufacturing cost of the testing socket increases substantially
Solution Approach 1:
The patent segments the data transmission function by equipping each testing socket with its own control chip that performs local data processing. This reduces the volume of data that needs to be transmitted through multiple ports, allowing the system to achieve high data transmission capacity while using fewer transmission ports per circuit board, thereby reducing manufacturing costs
Solution Approach 2:
The control chip on each testing socket performs self-service by autonomously processing and filtering test data locally. This self-processing capability reduces the data burden on transmission ports, enabling the system to maintain high data transmission capacity with fewer ports, thus lowering manufacturing costs
3Device complexity
If the testing equipment uses a single circuit board or testing socket, then the system structure is simplified, but the reliability decreases because a single failure shuts down the entire testing operation
Solution Approach 1:
The patent implements segmentation by creating multiple independent testing sockets, each with its own control chip and processing capability. This modular segmentation ensures that a failure in one testing socket does not affect others, maintaining testing operation continuity while preserving relatively simple system structure through standardized modular units
Solution Approach 2:
The patent changes the system architecture parameter from centralized to distributed control. By distributing processing capabilities across multiple independent testing sockets with individual control chips, the system achieves improved reliability and fault tolerance while maintaining structural simplicity through modular design
Data Source
AI summary
A testing equipment is provided, in which at least one testing module is disposed on a machine, and the testing module includes a circuit board, a testing carrier disposed on the circuit board and carrying a target object, and a processor disposed on the circuit board and electrically connected to the testing carrier, such that the testing module can operate and process a target information of the target object by itself via the processor, without connecting to an external computer to operate and process the target information of the target object, so as to quickly obtain a detecting information of the target object.