Distributed Program Sequencing in Programmable Microprocessor Cores
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Solution Overview
Problem
Existing processor architectures are not powerful or flexible enough to handle real-time universal multimedia applications, particularly in devices like cellular handsets, due to limitations in instruction set design, data flow, and memory access, leading to inefficiencies in computation and pipeline filling.
Innovation Solution
A processor design with distributed program sequencing, where each functional unit has its own program counter and local memory, using a common instruction set to code instruction sequencing and hardware controls, and connecting units through a full-access switch to maximize programmability and reduce bandwidth requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single centralized instruction set controls all functional blocks, then hardware control is simplified, but flexibility and programmability for diverse multimedia applications are reduced
Solution Approach 1:
The processor is divided into multiple independent functional units (FU0-FU7), each with its own program counter and local memory. This segmentation allows each unit to execute instructions independently, providing flexibility for diverse multimedia applications while maintaining simplified control within each unit.
Solution Approach 2:
The patent introduces a new dimension of control by allowing functional units to be configured in different operational modes (independent execution, synchronized execution, master-slave configuration). This dimensional change enables the same hardware structure to adapt to various application requirements without increasing control complexity.
2Adaptability or versatility
If functional blocks are made more flexible to execute general purpose programs, then adaptability improves, but the number of bits required to configure them increases
Solution Approach 1:
Each functional unit is designed as a universal block capable of performing multiple operations (arithmetic, logic, memory access) through configuration. This universality allows the same hardware to handle diverse multimedia applications without requiring dedicated configuration bits for each specific function.
Solution Approach 2:
The functional units can dynamically change their operational mode and configuration during execution. The program counter and local memory allow each unit to adapt its behavior based on the current instruction stream, reducing the need for static configuration bits while maintaining high flexibility.
3Productivity
If distributed program sequencing is implemented with each functional unit having its own program counter, then flexibility and parallel execution improve, but hardware complexity increases
Solution Approach 1:
The program sequencing functionality is segmented and distributed to each functional unit, with each unit having its own program counter and local memory. This segmentation enables parallel execution of multiple instruction streams while keeping each unit's internal structure simple and manageable.
Solution Approach 2:
The patent introduces a control unit that acts as an intermediary between the distributed functional units. This mediator coordinates the operation of multiple program counters and manages data flow between functional units, enabling parallel execution without requiring complex inter-unit communication protocols.
4Device complexity
If instruction flow and data flow are coupled in traditional architecture, then bandwidth utilization is simplified, but performance is limited by the Von Neumann bottleneck
Solution Approach 1:
The patent separates instruction flow and data flow into independent pathways. Each functional unit has its own local memory for instructions and can access external memory independently, eliminating the Von Neumann bottleneck by allowing simultaneous instruction fetching and data processing without contending for the same bandwidth.
Solution Approach 2:
The control unit serves as an intermediary that manages the decoupled instruction and data flows. It coordinates between the instruction memory, data memory, and functional units, ensuring efficient utilization of bandwidth while maintaining the benefits of separated instruction and data paths.
Data Source
AI summary
Improved instruction set and core design, control and communication for programmable microprocessors is disclosed, involving the strategy for replacing centralized program sequencing in present-day and prior art processors with a novel distributed program sequencing wherein each functional unit has its own instruction fetch and decode block, and each functional unit has its own local memory for program storage; and wherein computational hardware execution units and memory units are flexibly pipelined as programmable embedded processors with reconfigurable pipeline stages of different order in response to varying application instruction sequences that establish different configurations and switching interconnections of the hardware units.