Distributed Queue Multi-Bus Routing for Asynchronous Multi-CPU Chips
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Solution Overview
Problem
As chip density increases, synchronizing reliable data transfers based on a single clock becomes increasingly difficult, leading to poor performance and user experience.
Innovation Solution
Implementing a distributed queue multi-bus (DQMB) architecture on multi-CPU chips, utilizing multiple buses in pairs for upstream and downstream communication, with a grid layout and asynchronous operation, and employing Bellman-Ford shortest path algorithms for data routing and time division multiplexing to optimize data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If chip density is increased, then more transistors can be packed into smaller space, but synchronizing reliable data transfers based on a single clock becomes increasingly difficult
Solution Approach 1:
The patent segments the single clock system into multiple asynchronous clocks, each managing a specific region or component on the chip. This allows independent timing control for different parts of the chip, maintaining reliability even as density increases and signal propagation delays vary across the chip.
Solution Approach 2:
The patent introduces dynamic clock management where clocks can be enabled or disabled based on operational needs. The system dynamically adjusts which clocks are active and their frequencies, allowing flexible synchronization that adapts to varying data transfer requirements and chip density conditions.
2Quantity of substance
If chip density is increased, then more transistors can be packed into smaller space, but overall chip performance suffers
Solution Approach 1:
By segmenting the chip into regions with independent asynchronous clocks, the patent enables parallel data transfers across multiple regions simultaneously. This segmentation eliminates the bottleneck of a single global clock, allowing high-density chips to maintain high performance through concurrent operations.
Solution Approach 2:
The patent changes the timing parameter from a single fixed clock frequency to multiple variable frequencies. Each region can operate at its optimal frequency, and the system can dynamically adjust frequencies based on workload, maximizing chip performance despite increased density.
3Device complexity
If a single clock is used for data transfers, then synchronization is simple, but reliable data transfers become difficult as chip density increases
Solution Approach 1:
The patent divides the chip into segments, each with its own clock, simplifying the synchronization problem locally. Within each segment, data transfers are synchronized by the local clock, while inter-segment transfers are coordinated through message passing and handshaking protocols, achieving reliability without global synchronization complexity.
Solution Approach 2:
The patent introduces software or hardware intermediaries that coordinate data transfers between different clock domains. These intermediaries act as mediators that translate between different timing domains, ensuring reliable data transfer while keeping each local domain simple and independent.
Data Source
AI summary
Distributed queue multi-bus on multi-CPU chips is enabled. For example, a method can comprise generating, by a system comprising a processor, a reservation request for a bus between a source node and a destination node, based on the reservation request, adding, by the system, data applicable to the reservation request to a queue of a bus located between the source node and the destination node, using a defined data routing process, determining, by the system, a path between the source node and the destination node, and in response to the queue being determined to comprise no other reservation requests prior to the reservation request, sending, by the system, data from the source node to the destination node via the bus.