Distributed Reference Cells for Accurate Current Sensing in Memory Arrays
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Solution Overview
Problem
Charge trap memory cells in multiple time programmable memory arrays face read errors due to charge loss over time, leading to incorrect bit readings, and existing margin testing techniques can damage cells through repeated high voltage applications and are not sufficiently accurate.
Innovation Solution
A memory array with distributed charge trap reference cells and comparators that enable single-ended current sensing, using a margin testing technique to program cells while limiting overwriting, and optionally allowing de-programming, by varying wordline and reference wordline voltages to balance process variations and increase sensing accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If margin testing technique is used to program memory cells, then programming accuracy is improved, but cell damage increases due to repeated high voltage applications
Solution Approach 1:
The patent applies preliminary action by performing margin testing during the programming process to determine the exact point at which the memory cell has been sufficiently programmed. This allows the programming operation to stop at the optimal point rather than continuing with excessive high voltage applications, thereby achieving accurate programming while minimizing cell damage from repeated over-programming attempts.
2Measurement precision
If distributed reference cells are used for current sensing, then sensing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the memory array into multiple segments, each with its own reference cell and comparator circuit. This distributed architecture allows each segment to independently sense and compare currents, improving overall sensing accuracy through localized reference measurements while maintaining scalability across the entire array.
Solution Approach 2:
The patent uses copying by creating multiple identical reference cells distributed throughout the array, each serving as a local reference for its corresponding column. This approach improves sensing accuracy by providing matched reference conditions for each sensing operation while using standardized, repeatable cell designs that simplify fabrication.
3Reliability
If charge is injected into CTFET gate to program memory cell, then memory cell storage capability is improved, but charge loss over time increases leading to read errors
Solution Approach 1:
The patent applies feedback by continuously monitoring the current through the memory cell during programming using the distributed reference cells and comparators. This real-time feedback allows the system to detect when the desired charge level has been achieved and adjust subsequent programming pulses accordingly, preventing both under-programming and over-programming that would lead to charge loss and read errors.
Data Source
AI summary
An array of memory cells in rows and columns with each column having a corresponding reference cell and a corresponding comparator. Each memory cell in a given row and given column is connected to a memory wordline for the row and to a memory bitline for the column. Each reference cell is connected to a reference wordline for the reference cells and to a reference bitline. Each comparator for a column has a current mirror with a reference section connected to the reference bitline for the reference cell for the column and a memory section connected to the memory bitline for the memory cells in the column. Each reference section has a current mirror node and all current mirror nodes in the array are connected to reduce mismatch and improve sensing accuracy. Voltages applied to the memory and reference wordlines are varied to provide accurate single-ended sensing, margin testing, etc.