Distributed Register File Architecture for Low-Latency Parallel Processing
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Solution Overview
Problem
Existing processing architectures struggle with efficiently handling large, unstructured datasets due to inefficiencies in data processing and resource management, particularly in terms of energy consumption and data accessibility, which can overwhelm traditional systems.
Innovation Solution
A parallel processing architecture with distributed register files, utilizing a two-dimensional array of compute elements with virtual registers mapped to physical register files across the array, enabling parallel operation processing and fine-grained control through compiler-generated control words.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional centralized register files are used, then data accessibility is simplified, but data transfer latency increases and energy consumption increases
Solution Approach 1:
The patent divides the centralized register file into multiple distributed register files across different compute elements. Each compute element has local register files that store data locally, eliminating the need for long-distance data transfers to a centralized register file. This segmentation reduces data transfer latency while the systematic distribution strategy manages the increased architectural complexity.
Solution Approach 2:
The patent transitions from a single centralized register file architecture to a multi-dimensional distributed architecture where register files are spread across multiple compute elements in a two-dimensional array. This dimensional change allows data to be accessed locally at each compute element, dramatically reducing access latency while the regular distribution pattern provides structure to manage complexity.
2Use of energy by moving object
If data is stored in a centralized location, then access control is simplified, but energy consumption increases due to data transfer
Solution Approach 1:
The patent segments the centralized storage into distributed local register files at each compute element. This eliminates energy-consuming data transfers across the interconnect network by keeping data locally where computation occurs. The segmented architecture manages complexity through systematic distribution and local management at each compute element.
Solution Approach 2:
Each compute element maintains its own local register files, making it self-sufficient for data access without requiring communication with other compute elements or a centralized register file. This self-service approach eliminates energy-consuming data transfers while the standardized self-management across all compute elements keeps the system manageable despite distributed complexity.
3Productivity
If parallel processing is implemented, then throughput increases, but resource management complexity increases
Solution Approach 1:
The patent segments processing into multiple independent compute elements that operate in parallel, each with its own local register files. This segmentation enables simultaneous execution of multiple operations across different compute elements, increasing throughput. The systematic distribution of resources to each segment manages the complexity of parallel resource management.
Solution Approach 2:
Each compute element is designed as a universal processing unit with identical capabilities and local register files, allowing any compute element to perform any computation task. This universality simplifies resource management in parallel processing because the same management rules apply to all compute elements regardless of which specific element is executing which task, increasing throughput without proportionally increasing management complexity.
Data Source
AI summary
Techniques for task processing based on a parallel processing architecture with distributed register files are disclosed. A two-dimensional array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements. The array of compute elements is controlled on a cycle-by-cycle basis. The controlling is enabled by a stream of wide, variable length, control words generated by the compiler. Virtual registers are mapped to a plurality of physical register files distributed among one or more of the compute elements. Virtual registers are represented by the compiler. The mapping is performed by the compiler. A broadcast write operation is enabled to two or more of the physical register files. Operations contained in the control words are executed. Operations are enabled by at least one of the distributed physical register files. Implementation in separate compute elements enables parallel operation processing.