Distributed Row Decoder for Phase-Change Memory Leakage Control
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Solution Overview
Problem
Existing non-volatile phase-change memory devices using BJT transistors face issues with high leakage currents and power consumption due to undesired voltage drops along wordlines, which are exacerbated by the use of high biasing voltages, leading to inefficiencies in voltage management and increased power consumption.
Innovation Solution
A row-decoding architecture utilizing a shared pull-up stage with high-voltage PMOS transistors and local row-decoding stages with NMOS transistors, which decouple selected wordlines from ground and rapidly restore deselected wordlines to high voltage, minimizing leakage and power consumption while allowing for high-voltage operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If BJT transistors are used in the row decoder, then high-voltage operation is enabled, but leakage current and power consumption increase due to undesired voltage drops along wordlines
Solution Approach 1:
The row decoder is divided into multiple independent decoding stages distributed along the wordline. Each stage decodes a portion of the row address and drives a segment of the wordline, preventing cumulative voltage drops and reducing leakage current propagation across the entire wordline length.
Solution Approach 2:
Dummy transistors are introduced as intermediary elements between the decoding stages and the wordline. These dummy transistors act as buffers that isolate the active decoding circuitry from the wordline, preventing direct leakage paths while maintaining the high-voltage operation capability required for phase-change memory.
2Power
If high biasing voltages are applied to wordlines, then phase-change material switching is enabled, but voltage drops along wordlines increase, causing inefficiencies
Solution Approach 1:
The wordline is divided into multiple segments, each driven by a separate decoding stage. This segmentation ensures that high biasing voltages are applied locally only where needed for phase-change switching, rather than across the entire wordline length, thereby minimizing cumulative voltage drops and energy loss.
Solution Approach 2:
The distributed decoding stages prepare and apply the appropriate voltage levels to specific wordline segments before the phase-change switching operation occurs. This preliminary action ensures that high voltages are present only in the regions where memory cells are being accessed, avoiding unnecessary voltage application and associated energy losses in other regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces static and dynamic leakage, optimizes power consumption, and allows for efficient high-voltage operation without area overhead, enhancing the performance and reliability of non-volatile phase-change memory devices.
Implementation Method 1
A row-decoding architecture utilizing a shared pull-up stage with high-voltage PMOS transistors and local row-decoding stages with NMOS transistors, which decouple selected wordlines from ground and rapidly restore deselected wordlines to high voltage
Implementation Method 2
The proposed solution effectively reduces static and dynamic leakage, optimizes power consumption, and allows for efficient high-voltage operation
Implementation Method 3
The phase switching in a memory element may be obtained by locally increasing the temperature of the region of phase-change material, for example, by causing the passage of an electrical programming current through resistive electrodes (generally known as heaters) arranged in contact with the region of phase-change material. This electrical current, by the Joule effect, generates the temperature profile required for the phase change.
Data Source
AI summary
In an embodiment, a non-volatile memory device is proposed. The device includes a plurality of local pull-up stages distributed along a group of memory portions in a memory array. Each local pull-up stage includes, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type. The local pull-up transistors of each local pull-up are configured to locally decouple the corresponding wordline from a node at a first reference potential in response to a wordline that extends through the group of memory portions being selected, and locally couple the corresponding wordline to the node at the first reference potential in response to all the wordlines that extend through the group of memory portions being deselected to restore locally a deselection voltage on a wordline previously selected.