Distributed RS Interleaver for Low-Latency Burst Error Protection
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Solution Overview
Problem
Traditional block interleavers in wired communication systems introduce latency and require significant memory buffers, making them unsuitable for high-data-rate applications where they also necessitate parallel processing of multiple encoders running at slower speeds.
Innovation Solution
The implementation of a low-cost, low-latency interleaving physical layer (PHY) system that omits the use of memory buffers and employs a distributed Reed-Solomon (RS) encoder with a depth L, allowing each RS encoder to operate at a lower frequency, thereby reducing latency and cost while maintaining high throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional block interleaver is used to mitigate burst errors, then error protection capability is improved, but latency increases and memory buffer requirements increase
Solution Approach 1:
The patent divides the single long RS FEC code into L shorter RS FEC codes through distributed encoding across L encoders. This segmentation allows each encoder to operate independently at lower rates, reducing the memory buffer requirements and latency associated with traditional block interleavers while maintaining the same error protection capability against burst errors.
2Reliability
If traditional block interleaver is used to mitigate burst errors, then error protection capability is improved, but device complexity and cost increase due to memory buffer requirements
Solution Approach 1:
The patent segments the interleaving function into L distributed RS FEC encoders that operate in parallel. This eliminates the need for large memory buffers required by traditional block interleavers, reducing device complexity and cost while maintaining error protection capability.
Solution Approach 2:
The patent introduces L intermediate RS FEC encoders as mediators between the data source and the transmission channel. These encoders distribute the encoding task and eliminate the need for large memory buffers, serving as an intermediary solution that reduces complexity while maintaining reliability.
3Productivity
If higher data rate is achieved in communication systems, then throughput is improved, but traditional block interleaver requires parallel processing of multiple encoders running at slower speeds
Solution Approach 1:
The patent segments the high-rate encoding task into L parallel RS FEC encoders operating at lower individual rates. Each encoder processes a portion of the data stream, allowing the system to achieve high overall throughput while each individual encoder operates at a manageable, lower speed, reducing the complexity of parallel processing requirements.
Data Source
AI summary
An interleaved encoder includes a number of encoders consisting of L parallel encoders, and a first switch circuit to sequentially couple an input node to an input port of one of the encoders. The input node receives a group of K*L symbols. Each symbol of the group of K*L symbols is received in synch with a respective clock pulse of a group of K*L clock pulses. The first switch circuit is synched with clock pulses of the group of K*L clock pulses, and sequentially couples the input node to an input port of a subsequent one of the encoders in response to each clock pulse of the group of K*L clock pulses.