Distributed Scheduling System for FPGA Emulation Delay Modeling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In integrated circuit design, maintaining consistent delays across different FPGAs in emulation systems is challenging due to non-deterministic clocking events and the lack of synthesizable code for clock generators, leading to performance issues and design bugs.
Innovation Solution
A distributed scheduling system with a master scheduler and multiple schedulers is implemented, allowing for distributed clock generation and synchronization of delays across programmable devices, enabling the emulation of clock generators and improving performance by placing delays close to their original location in the design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If behavioral clock generator code is used to model non-periodic clocks, then clocking events can be generated with pseudo-random order, but the code is not HDL synthesizable and causes non-deterministic clocking events in physical hardware
Solution Approach 1:
The patent creates a hardware copy of the behavioral clock generator logic using programmable delay elements and schedulers. This hardware implementation replicates the pseudo-random clocking behavior while being synthesizable and deterministic in physical hardware, resolving the contradiction between modeling capability and determinism.
Solution Approach 2:
The patent replaces the software-based behavioral HDL code with a hardware-based implementation using programmable devices. This substitution allows the clock generator to be synthesized into physical hardware while maintaining the pseudo-random clocking behavior, eliminating the non-deterministic nature of the original HDL approach.
2Adaptability or versatility
If clock generators are distributed across multiple FPGAs, then scalability is improved, but maintaining consistent delays becomes difficult
Solution Approach 1:
The patent implements a feedback mechanism where each scheduler monitors its local delay values and communicates with the master scheduler. This feedback loop allows the system to detect and compensate for delay variations across distributed FPGAs, maintaining consistent timing while preserving scalability.
Solution Approach 2:
The patent dynamically adjusts delay parameters based on the actual timing conditions in each FPGA. By changing delay values in response to measured performance, the system maintains consistent delays across distributed devices without requiring fixed, rigid timing configurations.
3Measurement precision
If delays are placed close to their original location in the design, then emulation accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the delay distribution into two parts: logical placement (close to original location for accuracy) and physical implementation (consolidated in schedulers for manageability). This segmentation allows high emulation accuracy while keeping the actual hardware complexity controlled through centralized scheduling logic.
Data Source
AI summary
A hardware verification system according to one embodiment includes, in part, a plurality of programmable devices. The plurality of programmable devices include a master scheduler, a plurality of schedulers and a plurality of programmable delay elements. A first one of the plurality of schedulers is configured to receive one or more delay values associated with one or more of the plurality of delay elements. Each of the plurality of programmable delay elements corresponds to a delay. The first scheduler is further configured to send a parameter corresponding to the one or more delay values to the master scheduler, and generate one or more signals corresponding to the one or more delay elements in response to a control signal the first scheduler receives from the master scheduler.