Distributed Selection Circuit for Processor Instruction Issuance
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Solution Overview
Problem
In pipelined processors, the selection of instruction operations to issue to execution circuits during each clock cycle is a time-critical path, and existing unified selection circuits require a large number of logic gates, leading to increased chip area and power consumption, which can compromise throughput, especially at high clock rates.
Innovation Solution
Implementing a distributed selection circuit where each execution circuit has access to a subset of all operations, allowing the selection circuit to choose operations from one instruction queue to issue to another execution circuit if the corresponding queue is empty, thereby increasing throughput while reducing chip area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a unified selection circuit is used to select instructions for multiple execution units, then instruction selection can be centralized and simplified, but the number of logic gates increases leading to larger chip area and higher power consumption
Solution Approach 1:
The unified selection circuit is divided into multiple distributed selection circuits, each associated with a specific execution unit. Each distributed circuit only handles instruction selection for its associated execution unit, segmenting the large unified circuit into smaller independent units. This reduces the logic gates required in each individual circuit while maintaining overall selection functionality across multiple execution units.
Solution Approach 2:
The patent introduces a cross-queue selection mechanism where execution units can select instructions from alternative instruction queues when their primary queue is empty. This adds a dimensional aspect to instruction selection by allowing horizontal movement between queues, effectively increasing the instruction supply without requiring additional vertical selection logic gates.
2Device complexity
If a unified selection circuit is used to select instructions for multiple execution units, then instruction selection can be centralized and simplified, but power consumption increases
Solution Approach 1:
By segmenting the unified selection circuit into multiple distributed selection circuits, the total power consumption is reduced because each small circuit consumes less power than the large unified circuit would. The power consumption scales with the size of the logic gates, and multiple small circuits use fewer total gates than one large circuit.
Solution Approach 2:
The patent employs simpler, less resource-intensive selection circuits that are adequate for their specific purpose rather than using a complex unified circuit for all purposes. Each distributed selection circuit uses minimal logic gates appropriate for its specific execution unit, avoiding the overhead of a comprehensive unified design.
3Productivity
If the clock rate is increased to improve throughput, then more instructions can be completed per unit time, but the pipeline stage time becomes insufficient leading to selection bottlenecks
Solution Approach 1:
Segmenting the selection circuit into multiple distributed circuits allows parallel instruction selection to occur simultaneously for different execution units. This parallelism enables the processor to maintain high clock rates because each distributed circuit can complete its selection quickly without waiting for a centralized circuit to process all instructions sequentially.
Solution Approach 2:
Instructions are pre-loaded into multiple instruction queues before execution is needed. This preliminary action ensures that when the execution unit needs an instruction, multiple candidates are already available in the queues, allowing the selection circuit to quickly choose from pre-prepared options without time-consuming fetch operations during the critical clock cycle.
4Adaptability or versatility
If multiple instruction queues are used to store instruction operations, then instruction availability increases, but the selection circuit complexity increases
Solution Approach 1:
Each execution unit has its own distributed selection circuit that manages a subset of instruction queues. This segmentation means that while multiple queues exist system-wide, each individual selection circuit only needs to consider a portion of them, reducing the effective complexity at each decision point while maintaining overall system versatility through the collective capability of all distributed circuits.
Data Source
AI summary
Techniques are disclosed relating to selection circuitry configured to select instruction operations to issue to one or more execution circuits of a processor. In some embodiments, an apparatus includes a plurality of execution circuits configured to perform one or more instruction operations. The apparatus may further include a plurality of instruction queues configured to store information indicative of the one or more instruction operations. In some embodiments, the apparatus may include a selection circuit configured to select a first plurality of instruction operations from a first instruction queue. The selection circuit may be configured to select a first instruction operation from the first plurality of instruction operations to issue to a first execution circuits. Further, the selection circuit may be configured to select a predesignated instruction operation of the first plurality of instruction operations to issue to a second execution circuit in response to a determination that no instruction operations in a second instruction queue are available to issue.